[v2] riscv: Add K230 DDR controller and PHY models

[PATCH v2 0/3] riscv: Add K230 DDR controller and PHY models

Junze Cao posted 3 patches 1 month, 3 weeks ago

Diff against v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260807-k230-ddr-v2-v2-0-c531308ae819@gmail.com

Maintainers: Chao Liu <chao.liu@processmission.com>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>

MAINTAINERS                 |   3 +
docs/system/riscv/k230.rst  |   4 +
hw/misc/k230_ddr.c          | 556 ++++++++++++++++++++++++++++++++++++++++++++
hw/misc/meson.build         |   1 +
hw/riscv/k230.c             |  19 +-
include/hw/misc/k230_ddr.h  |  59 +++++
include/hw/riscv/k230.h     |   4 +
tests/qtest/k230-ddr-test.c | 226 ++++++++++++++++++
tests/qtest/meson.build     |   3 +-
9 files changed, 871 insertions(+), 4 deletions(-)

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[PATCH v2 0/3] riscv: Add K230 DDR controller and PHY models

Posted by Junze Cao 1 month, 3 weeks ago

The K230 SDK U-Boot SPL initializes DRAM by programming the DDRC CFG
and DDR PHY MMIO regions. The k230 machine currently exposes the DDR
configuration region as unimplemented and does not provide the PHY, so
the SPL cannot complete the training and DFI handshakes.

Add minimal models for the register behavior exercised by the SDK SPL.
The controller model provides reset values, register access policy, DFI
and software-update handshakes, and the Init-to-Normal transition. The
PHY model provides CSR ownership, the training mailbox, and DFI
completion. Wire both devices into the k230 machine and document the
resulting SPL support.

These device models allow firmware to complete the DDR initialization
sequence.

Changes in v2:

* Add LOG_UNIMP messages for unimplemented DDR PHY register accesses,
  including reads returning zero and ignored writes.

Testing performed:

* scripts/checkpatch.pl --branch upstream/master..HEAD
* meson test -C build --print-errorlogs
  qemu:qtest-riscv64/k230-ddr-test (6 subtests passed)
* Booted the K230 SDK U-Boot SPL through DDR initialization to its SPI
  boot path

---
Junze Cao (3):
      hw/misc: Add K230 DDR controller and PHY models
      hw/riscv: Connect K230 DDR controller and PHY models
      tests/qtest: Add K230 DDR controller tests

 MAINTAINERS                 |   3 +
 docs/system/riscv/k230.rst  |   4 +
 hw/misc/k230_ddr.c          | 556 ++++++++++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build         |   1 +
 hw/riscv/k230.c             |  19 +-
 include/hw/misc/k230_ddr.h  |  59 +++++
 include/hw/riscv/k230.h     |   4 +
 tests/qtest/k230-ddr-test.c | 226 ++++++++++++++++++
 tests/qtest/meson.build     |   3 +-
 9 files changed, 871 insertions(+), 4 deletions(-)
---
base-commit: 3e3ccab106f879b1512f8e0d51a827dd4de30e22
change-id: 20260807-k230-ddr-v2-f8037b6ac237

Best regards,
--  
Junze Cao <caojunze424@gmail.com>

Re: [PATCH v2 0/3] riscv: Add K230 DDR controller and PHY models

Posted by Alistair 1 month, 2 weeks ago

On Fri, 2026-08-07 at 18:21 +0800, Junze Cao wrote:
> The K230 SDK U-Boot SPL initializes DRAM by programming the DDRC CFG
> and DDR PHY MMIO regions. The k230 machine currently exposes the DDR
> configuration region as unimplemented and does not provide the PHY,
> so
> the SPL cannot complete the training and DFI handshakes.
> 
> Add minimal models for the register behavior exercised by the SDK
> SPL.
> The controller model provides reset values, register access policy,
> DFI
> and software-update handshakes, and the Init-to-Normal transition.
> The
> PHY model provides CSR ownership, the training mailbox, and DFI
> completion. Wire both devices into the k230 machine and document the
> resulting SPL support.
> 
> These device models allow firmware to complete the DDR initialization
> sequence.
> 
> Changes in v2:
> 
> * Add LOG_UNIMP messages for unimplemented DDR PHY register accesses,
>   including reads returning zero and ignored writes.
> 
> Testing performed:
> 
> * scripts/checkpatch.pl --branch upstream/master..HEAD
> * meson test -C build --print-errorlogs
>   qemu:qtest-riscv64/k230-ddr-test (6 subtests passed)
> * Booted the K230 SDK U-Boot SPL through DDR initialization to its
> SPI
>   boot path
> 
> ---
> Junze Cao (3):
>       hw/misc: Add K230 DDR controller and PHY models
>       hw/riscv: Connect K230 DDR controller and PHY models
>       tests/qtest: Add K230 DDR controller tests

Thanks!

Applied to riscv-to-apply.next

Alistair

> 
>  MAINTAINERS                 |   3 +
>  docs/system/riscv/k230.rst  |   4 +
>  hw/misc/k230_ddr.c          | 556
> ++++++++++++++++++++++++++++++++++++++++++++
>  hw/misc/meson.build         |   1 +
>  hw/riscv/k230.c             |  19 +-
>  include/hw/misc/k230_ddr.h  |  59 +++++
>  include/hw/riscv/k230.h     |   4 +
>  tests/qtest/k230-ddr-test.c | 226 ++++++++++++++++++
>  tests/qtest/meson.build     |   3 +-
>  9 files changed, 871 insertions(+), 4 deletions(-)
> ---
> base-commit: 3e3ccab106f879b1512f8e0d51a827dd4de30e22
> change-id: 20260807-k230-ddr-v2-f8037b6ac237
> 
> Best regards,
> --  
> Junze Cao <caojunze424@gmail.com>
>