[PATCH 0/5] target/riscv: support Debug 0.13 and 1.0

Daniel Henrique Barboza posted 5 patches 2 weeks, 6 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260805182506.2943757-1-daniel.barboza@oss.qualcomm.com
Maintainers: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>
docs/specs/index.rst              |  1 +
docs/specs/riscv-debug.rst        | 68 +++++++++++++++++++++++++++++++
target/riscv/cpu.c                | 21 +++++++---
target/riscv/cpu_cfg_fields.h.inc |  1 +
target/riscv/machine.c            |  2 +-
target/riscv/tcg/csr.c            |  2 +-
target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
target/riscv/tcg/debug.h          |  6 ++-
target/riscv/tcg/tcg-cpu.c        |  3 +-
9 files changed, 142 insertions(+), 13 deletions(-)
create mode 100644 docs/specs/riscv-debug.rst
[PATCH 0/5] target/riscv: support Debug 0.13 and 1.0
Posted by Daniel Henrique Barboza 2 weeks, 6 days ago
Hi,

This short series adds support for Debug 0.13 and Debug 1.0.  The
motivation is simple: we need Debug 1.0 to complete tue upstreaming of
sdext, which is already fully reviewed and acked for awhile [1], and
then proceed with the upstreaming of the RISC-V Server Ref board
(currently on v8: [2]).

The work is based in section 1.2.1.2 "Incompatible Changes from 0.13 to
1.0" of the ratified 1.0 spec [3].  It ended being simpler than
anticipated because we don't implement most of the registers/bits that
are backwards incompatible.  I added doc changes to explain the
rationale used.

After this series:

- 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers to
  Debug 0.13;
- setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
  precedence.

My hope is that this split will make it easier to to move away from
Debug 0.13 in the future once there's no more demand for it.

Patches based on master.

[1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
[2] https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
[3] https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf

Daniel Henrique Barboza (5):
  target/riscv: split 'debug' and 'sdtrig' flags
  target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
  target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
  target/riscv/tcg/debug: set tinfo version if sdtrig enabled
  docs/specs: add RISC-V CPU Debug support info

 docs/specs/index.rst              |  1 +
 docs/specs/riscv-debug.rst        | 68 +++++++++++++++++++++++++++++++
 target/riscv/cpu.c                | 21 +++++++---
 target/riscv/cpu_cfg_fields.h.inc |  1 +
 target/riscv/machine.c            |  2 +-
 target/riscv/tcg/csr.c            |  2 +-
 target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
 target/riscv/tcg/debug.h          |  6 ++-
 target/riscv/tcg/tcg-cpu.c        |  3 +-
 9 files changed, 142 insertions(+), 13 deletions(-)
 create mode 100644 docs/specs/riscv-debug.rst

-- 
2.43.0
Re: [PATCH 0/5] target/riscv: support Debug 0.13 and 1.0
Posted by Alistair Francis 1 day, 12 hours ago
On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> Hi,
> 
> This short series adds support for Debug 0.13 and Debug 1.0.  The
> motivation is simple: we need Debug 1.0 to complete tue upstreaming
> of
> sdext, which is already fully reviewed and acked for awhile [1], and
> then proceed with the upstreaming of the RISC-V Server Ref board
> (currently on v8: [2]).
> 
> The work is based in section 1.2.1.2 "Incompatible Changes from 0.13
> to
> 1.0" of the ratified 1.0 spec [3].  It ended being simpler than
> anticipated because we don't implement most of the registers/bits
> that
> are backwards incompatible.  I added doc changes to explain the
> rationale used.
> 
> After this series:
> 
> - 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers
> to
>   Debug 0.13;
> - setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
>   precedence.
> 
> My hope is that this split will make it easier to to move away from
> Debug 0.13 in the future once there's no more demand for it.
> 
> Patches based on master.
> 
> [1]
> https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
> [2]
> https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
> [3]
> https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf
> 
> Daniel Henrique Barboza (5):
>   target/riscv: split 'debug' and 'sdtrig' flags
>   target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
>   target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
>   target/riscv/tcg/debug: set tinfo version if sdtrig enabled
>   docs/specs: add RISC-V CPU Debug support info

Thanks!

Applied to riscv-to-apply.next

Alistair

> 
>  docs/specs/index.rst              |  1 +
>  docs/specs/riscv-debug.rst        | 68
> +++++++++++++++++++++++++++++++
>  target/riscv/cpu.c                | 21 +++++++---
>  target/riscv/cpu_cfg_fields.h.inc |  1 +
>  target/riscv/machine.c            |  2 +-
>  target/riscv/tcg/csr.c            |  2 +-
>  target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
>  target/riscv/tcg/debug.h          |  6 ++-
>  target/riscv/tcg/tcg-cpu.c        |  3 +-
>  9 files changed, 142 insertions(+), 13 deletions(-)
>  create mode 100644 docs/specs/riscv-debug.rst
Re: [PATCH 0/5] target/riscv: support Debug 0.13 and 1.0
Posted by Daniel Henrique Barboza 6 days, 6 hours ago
Ping


This is the series I talked about in our call last night/earlier today.

The v9 of the riscv-server-ref work was rebased on top of it, along with Chao's
sdext patches.  As soon as we get this queued I think I'll re-send Chao's
work next.


Cheers,
Daniel

On 8/5/2026 3:25 PM, Daniel Henrique Barboza wrote:
> Hi,
> 
> This short series adds support for Debug 0.13 and Debug 1.0.  The
> motivation is simple: we need Debug 1.0 to complete tue upstreaming of
> sdext, which is already fully reviewed and acked for awhile [1], and
> then proceed with the upstreaming of the RISC-V Server Ref board
> (currently on v8: [2]).
> 
> The work is based in section 1.2.1.2 "Incompatible Changes from 0.13 to
> 1.0" of the ratified 1.0 spec [3].  It ended being simpler than
> anticipated because we don't implement most of the registers/bits that
> are backwards incompatible.  I added doc changes to explain the
> rationale used.
> 
> After this series:
> 
> - 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers to
>    Debug 0.13;
> - setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
>    precedence.
> 
> My hope is that this split will make it easier to to move away from
> Debug 0.13 in the future once there's no more demand for it.
> 
> Patches based on master.
> 
> [1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
> [2] https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
> [3] https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf
> 
> Daniel Henrique Barboza (5):
>    target/riscv: split 'debug' and 'sdtrig' flags
>    target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
>    target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
>    target/riscv/tcg/debug: set tinfo version if sdtrig enabled
>    docs/specs: add RISC-V CPU Debug support info
> 
>   docs/specs/index.rst              |  1 +
>   docs/specs/riscv-debug.rst        | 68 +++++++++++++++++++++++++++++++
>   target/riscv/cpu.c                | 21 +++++++---
>   target/riscv/cpu_cfg_fields.h.inc |  1 +
>   target/riscv/machine.c            |  2 +-
>   target/riscv/tcg/csr.c            |  2 +-
>   target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
>   target/riscv/tcg/debug.h          |  6 ++-
>   target/riscv/tcg/tcg-cpu.c        |  3 +-
>   9 files changed, 142 insertions(+), 13 deletions(-)
>   create mode 100644 docs/specs/riscv-debug.rst
>
Re: [PATCH 0/5] target/riscv: support Debug 0.13 and 1.0
Posted by Chao Liu 2 days, 13 hours ago
Hi Daniel,

On Thu, Aug 20, 2026 at 08:01:39AM +0800, Daniel Henrique Barboza wrote:
> Ping
> 
> 
> This is the series I talked about in our call last night/earlier today.
> 
> The v9 of the riscv-server-ref work was rebased on top of it, along with Chao's
> sdext patches.  As soon as we get this queued I think I'll re-send Chao's
> work next.
Thanks for continuing to drive the sdext work. I don’t have much time to dedicate
to it at the moment, but I’ll do my best to help with the review.

Cheers,
Chao
> 
> 
> Cheers,
> Daniel
> 
> On 8/5/2026 3:25 PM, Daniel Henrique Barboza wrote:
> > Hi,
> > 
> > This short series adds support for Debug 0.13 and Debug 1.0.  The
> > motivation is simple: we need Debug 1.0 to complete tue upstreaming of
> > sdext, which is already fully reviewed and acked for awhile [1], and
> > then proceed with the upstreaming of the RISC-V Server Ref board
> > (currently on v8: [2]).
> > 
> > The work is based in section 1.2.1.2 "Incompatible Changes from 0.13 to
> > 1.0" of the ratified 1.0 spec [3].  It ended being simpler than
> > anticipated because we don't implement most of the registers/bits that
> > are backwards incompatible.  I added doc changes to explain the
> > rationale used.
> > 
> > After this series:
> > 
> > - 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers to
> >    Debug 0.13;
> > - setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
> >    precedence.
> > 
> > My hope is that this split will make it easier to to move away from
> > Debug 0.13 in the future once there's no more demand for it.
> > 
> > Patches based on master.
> > 
> > [1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
> > [2] https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
> > [3] https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf
> > 
> > Daniel Henrique Barboza (5):
> >    target/riscv: split 'debug' and 'sdtrig' flags
> >    target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
> >    target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
> >    target/riscv/tcg/debug: set tinfo version if sdtrig enabled
> >    docs/specs: add RISC-V CPU Debug support info
> > 
> >   docs/specs/index.rst              |  1 +
> >   docs/specs/riscv-debug.rst        | 68 +++++++++++++++++++++++++++++++
> >   target/riscv/cpu.c                | 21 +++++++---
> >   target/riscv/cpu_cfg_fields.h.inc |  1 +
> >   target/riscv/machine.c            |  2 +-
> >   target/riscv/tcg/csr.c            |  2 +-
> >   target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
> >   target/riscv/tcg/debug.h          |  6 ++-
> >   target/riscv/tcg/tcg-cpu.c        |  3 +-
> >   9 files changed, 142 insertions(+), 13 deletions(-)
> >   create mode 100644 docs/specs/riscv-debug.rst
> > 
>