[v1] target/riscv: Fix seed CSR sign extension

[PATCH 0/2] target/riscv: Fix seed CSR sign extension

Ivan Efremov posted 2 patches 1 month, 3 weeks ago

Diff against v1
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git fetch https://github.com/patchew-project/qemu tags/patchew/20260802000048.691333-1-nendensu@ispras.ru

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>

There is a newer version of this series

target/riscv/cpu_bits.h      | 10 +++++-----
tests/qtest/riscv-csr-test.c | 26 ++++++++++++++++++++++++++
2 files changed, 31 insertions(+), 5 deletions(-)

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[PATCH 0/2] target/riscv: Fix seed CSR sign extension

Posted by Ivan Efremov 1 month, 3 weeks ago

The seed CSR value on RV64 was sign extended while converting to target_ulong.

The first patch makes SEED_OPST_* unsigned.
The second patch adds qtest to check that upper 32 bits are zero.

Tests ran:
- riscv-csr-test
- make check: 324 passed, 11 skipped
- RISC-V Zkr-00 architectural test

Ivan Efremov (2):
  target/riscv: Fix seed CSR sign extension
  tests/qtest: Add seed CSR zero extension test

 target/riscv/cpu_bits.h      | 10 +++++-----
 tests/qtest/riscv-csr-test.c | 26 ++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 5 deletions(-)

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2.43.0