Hello,

This series adds a reusable Synopsys DesignWare SSI controller model and
uses it to model the three SSI instances on the Kendryte K230 machine.

This series supersedes the previous K230-specific SSI series:

  https://lore.kernel.org/qemu-devel/cover.1785064312.git.flamboyant.h.01@gmail.com/

Following review of v1, the controller has been split into a reusable
DesignWare SSI model and a K230 integration layer. The controller no longer
depends on K230 types, addresses, or HI_SYS state. K230-specific instance
profiles, MMIO mapping, PLIC routing, and flash attachment now live in the
K230 machine code.

The v1 implementation combined DesignWare SSI behaviour and K230-specific
SoC integration in one device. That made the reuse boundary unclear for
other SoCs using the same IP. This revision makes that boundary explicit:
the generic model implements the documented controller behaviour, while the
K230 machine supplies only its instance configuration and SoC connections.

The implemented controller scope is deliberately limited to Standard
single-line SPI PIO: configurable chip selects and FIFO depth, four TMOD
modes, FIFO and status handling, Standard interrupt state, and migration
state for the implemented data path. Enhanced SPI, internal DMA/IDMA, and
XIP transactions are deferred to follow-up series.

K230 has nine SSI interrupt source lines per instance. This series wires all
nine lines to preserve the documented PLIC topology. TXU, DONE, and AXIE
remain deasserted because their transfer engines are outside the Standard
PIO scope modeled here.

The final patch adds an optional M25P80-compatible SPI NOR flash on logical
spi0 CS0. It supports and tests Standard 1-1-1 accesses only; the enhanced
SPI and IDMA boot paths are outside the scope of this series.

Changes since v1:

* Replace the K230-specific controller type with a reusable DesignWare SSI
  model configured through num-cs, fifo-depth, and imr-reset properties.
* Keep K230 instance profiles, MMIO mapping, PLIC routing, and flash
  attachment in the K230 machine code.
* Limit this revision to Standard PIO, FIFO, interrupt, and 1-1-1 SPI NOR
  support; defer enhanced SPI, internal DMA/IDMA, and XIP to follow-up
  series.

Testing on the current V2 development tree:

* riscv64-softmmu build succeeds.
* K230 SSI qtest: 14/14 pass, covering register/reset contracts, Standard
  PIO TMOD modes, FIFO behaviour, interrupt state, PLIC routing, Standard
  1-1-1 flash identification and fixed-address reads, and
  unsupported-register semantics.
* U-Boot Standard SPI payload boot: U-Boot loads OpenSBI, Linux, initramfs,
  and the DTB from a W25Q256 flash and reaches a Linux initramfs shell.
  Standard sf probe, erase, write, readback, and compare also pass.
* Linux 5.10.4 Standard SPI PIO: dw_spi_mmio and spi-nor probe successfully;
  the MTD test partition completes erase, write, readback, and byte-wise
  comparison (K230_MTD_TEST_PASS mode=standard).

Kangjie Huang (5):
  hw/ssi: Add Synopsys DesignWare SSI standard PIO controller
  hw/ssi: Add DesignWare SSI standard interrupt support
  hw/riscv/k230: Instantiate DesignWare SSI controllers
  hw/riscv/k230: Route SSI interrupts to the PLIC
  hw/riscv/k230: Attach a standard SPI NOR flash

 docs/system/riscv/k230.rst     |    2 +
 hw/riscv/Kconfig               |    2 +
 hw/riscv/k230.c                |  178 +++++-
 hw/ssi/Kconfig                 |    4 +
 hw/ssi/dw_ssi.c                | 1083 ++++++++++++++++++++++++++++++++
 hw/ssi/meson.build             |    1 +
 include/hw/riscv/k230.h        |    7 +
 include/hw/ssi/dw_ssi.h        |   78 +++
 tests/qtest/k230-dw-ssi-test.c |  569 +++++++++++++++++
 tests/qtest/meson.build        |    4 +-
 10 files changed, 1912 insertions(+), 16 deletions(-)
 create mode 100644 hw/ssi/dw_ssi.c
 create mode 100644 include/hw/ssi/dw_ssi.h
 create mode 100644 tests/qtest/k230-dw-ssi-test.c

-- 
2.43.0