The previously independent threads for l2vic and qtimer are now combined,
which seems to make the most sense because qtimer testing effectively
depends on l2vic.

* split the hex-subsys refactor into 5 patches, one per field moved.
* add virtio_mmio[VIRTIO_DEV_COUNT] to HexagonVirtMachineState and record
each transport

l2vic changes in v4:
* INT_STATUSn and SOFT_INTn get L2VIC_OP_NONE; SOFT_INTn no longer
  writes int_enable as a side effect.
* SOFT_INTn now walks every set bit instead of only the lowest one.
* get_vid_group() rejects an out-of-range vid with LOG_GUEST_ERROR.
* fastl2vic region gains a read handler returning 0 (was write-only).
* Comments rewritten to describe the INT_GRPn interleave and VID packing.

qtimer changes in v4:
* hex_timer_rearm() uses muldiv64_round_up() instead of muldiv64()+1 ns.
* AC CNTFRQ write of 0 is rejected with LOG_GUEST_ERROR.
* realize() validates freq_hz != 0 and frame_stride a nonzero power of 2.
* Frame decode drops the redundant offset mask now that stride is
guaranteed to be a power of two.
* Reset clears cntpl0acr and deasserts the frame IRQ.
* vmstate adds freq_hz and secure.

wiring changes in v4:
* hex_subsys_add_cpu() splits CPU parenting/link wiring from realize;
machines now realize the cluster before the CPUs.
* qtimer AC region was unintentionally unmapped, now mapped at m_cfg->csr_base.

test changes in v4:
* l2vic-test: adds VID_GRP_0..3 readback and an l2vic_set_vid_group()
helper; VID steering now checked per output line rather than by
writing INT_GRPn_1..3 directly.
* l2vic-test: multiple-pending case drains in a loop instead of a single
clear, and restores INT_GRPn_0/INT_TYPEn between blocks.
* qct-qtimer-test: adds test_qtimer_ac_region() covering CNTFRQ (incl.
the ignored 0 write), CNTSR, CNTTID_0 and CNTACR frame 0.

Lacking R-b:
 - hw/hexagon: add hex-subsys
 - hw/hexagon: move VTCM to the common machine state
 - hw/hexagon: move global registers to hex-subsys
 - hw/hexagon: move the TLB to hex-subsys
 - hw/hexagon: group the CPUs in a cluster
 - hw/hexagon/virt: add l2vic interrupt-controller and virtio-mmio FDT nodes
 - hw/timer: Add QCT QTimer device model
 - hw/hexagon: connect qtimer device
 - tests/qtest: add qct-qtimer qtest
 - tests/functional/hexagon: enable more arch_tests cases


l2vic v3: https://lore.kernel.org/qemu-devel/20260724183648.190531-1-brian.cain@oss.qualcomm.com/
l2vic v2: https://lore.kernel.org/qemu-devel/20260715185701.1287176-1-brian.cain@oss.qualcomm.com/
l2vic v1: https://lore.kernel.org/qemu-devel/20260714155126.3509544-1-brian.cain@oss.qualcomm.com/
qtimer v1: https://lore.kernel.org/qemu-devel/20260718013241.1550124-1-brian.cain@oss.qualcomm.com/

Brian Cain (17):
  hw/hexagon: add hex-subsys
  hw/hexagon: move VTCM to the common machine state
  hw/hexagon: move global registers to hex-subsys
  hw/hexagon: move the TLB to hex-subsys
  hw/hexagon: group the CPUs in a cluster
  bitops.h: Add find_first_bit32()
  hw/hexagon: extract get_reg_value/set_reg_value stubs in globalreg
  hw/hexagon: connect l2vic device
  hw/hexagon/virt: instantiate virtio-mmio transports
  hw/hexagon/virt: add l2vic interrupt-controller and virtio-mmio FDT
    nodes
  hw/hexagon/virt: connect pl011 UART interrupt
  tests/qtest: add L2VIC qtest
  tests/functional/hexagon: add arch_tests functional test
  hw/timer: Add QCT QTimer device model
  hw/hexagon: connect qtimer device
  tests/qtest: add qct-qtimer qtest
  tests/functional/hexagon: enable more arch_tests cases

Sid Manning (1):
  hw/intc: Add l2vic interrupt controller

 MAINTAINERS                                 |   7 +
 docs/devel/hexagon-l2vic.rst                |  55 ++
 docs/devel/index-internals.rst              |   1 +
 include/hw/hexagon/hex-subsys.h             |  32 +
 include/hw/hexagon/hexagon.h                |   6 +
 include/hw/hexagon/hexagon_globalreg.h      |   8 +
 include/hw/hexagon/virt.h                   |   4 +-
 include/hw/intc/hex-l2vic.h                 |  61 ++
 include/hw/timer/qct-qtimer.h               |  43 ++
 include/qemu/bitops.h                       |  30 +-
 target/hexagon/cpu.h                        |   2 +
 hw/hexagon/hex-subsys.c                     | 176 +++++
 hw/hexagon/hexagon_dsp.c                    |  45 +-
 hw/hexagon/hexagon_globalreg.c              |  65 +-
 hw/hexagon/virt.c                           | 130 ++--
 hw/intc/hex-l2vic.c                         | 556 ++++++++++++++++
 hw/timer/qct-qtimer.c                       | 681 ++++++++++++++++++++
 target/hexagon/cpu.c                        |   2 +
 target/hexagon/op_helper.c                  |  16 +-
 tests/qtest/l2vic-test.c                    | 249 +++++++
 tests/qtest/qct-qtimer-test.c               | 269 ++++++++
 hw/hexagon/Kconfig                          |   3 +
 hw/hexagon/meson.build                      |   1 +
 hw/intc/Kconfig                             |   3 +
 hw/intc/meson.build                         |   2 +
 hw/intc/trace-events                        |   4 +
 hw/timer/Kconfig                            |   3 +
 hw/timer/meson.build                        |   2 +
 hw/timer/trace-events                       |   5 +
 tests/functional/hexagon/test_arch_tests.py |  38 ++
 tests/qtest/meson.build                     |   2 +-
 31 files changed, 2411 insertions(+), 90 deletions(-)
 create mode 100644 docs/devel/hexagon-l2vic.rst
 create mode 100644 include/hw/hexagon/hex-subsys.h
 create mode 100644 include/hw/intc/hex-l2vic.h
 create mode 100644 include/hw/timer/qct-qtimer.h
 create mode 100644 hw/hexagon/hex-subsys.c
 create mode 100644 hw/intc/hex-l2vic.c
 create mode 100644 hw/timer/qct-qtimer.c
 create mode 100644 tests/qtest/l2vic-test.c
 create mode 100644 tests/qtest/qct-qtimer-test.c

-- 
2.34.1