target/i386: Add AMD LBR Extension v2 support

[PATCH 0/2] target/i386: Add AMD LBR Extension v2 support

Shivansh Dhiman posted 2 patches 9 hours ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260724201203.633799-1-shivansh.dhiman@amd.com

Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Zhao Liu <zhao1.liu@intel.com>

target/i386/cpu.c | 26 +++++++++++++++++++++++---
target/i386/cpu.h |  4 +++-
2 files changed, 26 insertions(+), 4 deletions(-)

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[PATCH 0/2] target/i386: Add AMD LBR Extension v2 support

Posted by Shivansh Dhiman 9 hours ago

LbrExtV2, introduced on Zen 4, is a branch sampling facility providing a
16-entry stack of last-taken branches via dedicated MSRs:
  * MSR 0xC000010E - Last Branch Stack Select  (LBR_SELECT)
  * MSR 0xC000010F - Debug Extension Control   (DBG_EXTN_CFG)
  * MSR 0xC0010300..0xC001031F - 16 LBR FROM/TO MSR pairs

This QEMU series exposes AMD's Last Branch Record Extension v2 (LbrExtV2) and
the dependent LBR freeze feature to guests, so they can use the LBR v2
virtualization provided by KVM.

The related KVM patches for this feature can be found at [1].

[1] https://lore.kernel.org/kvm/20260724195040.630468-1-shivansh.dhiman@amd.com/

This series is based on top of stable-11.0 (tag: v11.0.1) branch.

Regards,
Shivansh

---
Shivansh Dhiman (2):
  target/i386: Add support for AMD LbrExtV2
  target/i386: Add support for AMD LBR/PMC freeze

 target/i386/cpu.c | 26 +++++++++++++++++++++++---
 target/i386/cpu.h |  4 +++-
 2 files changed, 26 insertions(+), 4 deletions(-)


base-commit: 6e9a825c1d4e7b62d072e99a89ecd1a74c7f0d55
-- 
2.43.0