Allow tgen_brcondi to choose between TBNZ and TST+B.cond for
implementing a particular mask.
Suggested-by: yujun <yujun@kylinos.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Supercedes: 20260629111602.282742-1-yujun@kylinos.cn
("[PATCH] tcg/aarch64: Use TBNZ for 16-byte alignment check on i128 ld/st")
Let tgen_brcondi do the heavy lifting, rather than open-coding it all.
r~
---
tcg/aarch64/tcg-target.c.inc | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index cc9c2a5158..1f9678438d 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1889,23 +1889,18 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
use_pair = h.aa.atom < MO_128 || have_lse2;
if (!use_pair) {
- tcg_insn_unit *branch = NULL;
+ TCGLabel *label = NULL;
TCGReg ll, lh, sl, sh;
-
/*
- * If we have already checked for 16-byte alignment, that's all
- * we need. Otherwise we have determined that misaligned atomicity
- * may be handled with two 8-byte loads.
+ * Check for 16-byte alignment, taking into consideration the
+ * alignment that has already been checked.
*/
- if (h.aa.align < MO_128) {
- /*
- * TODO: align should be MO_64, so we only need test bit 3,
- * which means we could use TBNZ instead of ANDS+B_C.
- */
- tcg_out_logicali(s, Ilogic_imm_ANDSI, 0, TCG_REG_XZR, addr_reg,
- 15);
- branch = s->code_ptr;
- tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);
+ int a_mask = 16 - (1 << h.aa.align);
+
+ if (a_mask > 0) {
+ label = gen_new_label();
+ tgen_brcondi(s, TCG_TYPE_I32, TCG_COND_TSTNE,
+ addr_reg, a_mask, label);
use_pair = true;
}
@@ -1944,7 +1939,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
if (use_pair) {
/* "b .+8", branching across the one insn of use_pair. */
tcg_out_insn(s, branch, B, 2);
- reloc_pc19(branch, tcg_splitwx_to_rx(s->code_ptr));
+ tcg_out_label(s, label);
}
}
--
2.43.0