target/arm: Implement FEAT_SME2p2

[PATCH for-11.2 0/6] target/arm: Implement FEAT_SME2p2

Richard Henderson posted 6 patches 5 days, 18 hours ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260719174905.420725-1-richard.henderson@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Laurent Vivier <laurent@vivier.eu>, Helge Deller <deller@gmx.de>

target/arm/cpu-features.h      |   5 +
linux-user/aarch64/elfload.c   |   2 +
target/arm/tcg/cpu64.c         |   5 +-
target/arm/tcg/translate-sme.c | 180 ++++++++++++++++++---------------
docs/system/arm/emulation.rst  |   2 +
target/arm/tcg/sme.decode      | 118 ++++++++++++++++-----
6 files changed, 201 insertions(+), 111 deletions(-)

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[PATCH for-11.2 0/6] target/arm: Implement FEAT_SME2p2

Posted by Richard Henderson 5 days, 18 hours ago

Based-on: 20260713230244.70174-1-richard.henderson@linaro.org
("[PATCH for-11.2 00/10] target/arm: Implement FEAT_SME_TMOP")

One final pair of insns, FMUL (multiple and single vectors) and
FMUL (multiple vectors), which are not covered by a sub-feature.

Finishing SME2p2 allows us to finally enable SVE2p2 in -cpu max.


r~


Richard Henderson (6):
  target/arm: Split zdn in do_z2z_n1 and do_z2z_n1_fpst
  target/arm: Split zdn in do_z2z_nn and do_z2z_nn_fpst
  target/arm: Fix b16b16 feature test for SME2 BFCLAMP, BFMAX, BFMIN
  target/arm: Split decode of BFloat SME FMAX/FMIN
  target/arm: Implement FMUL (multiple/multiple and single vectors)
  target/arm: Enable FEAT_SVE2p2 and FEAT_SME2p2 for -cpu max

 target/arm/cpu-features.h      |   5 +
 linux-user/aarch64/elfload.c   |   2 +
 target/arm/tcg/cpu64.c         |   5 +-
 target/arm/tcg/translate-sme.c | 180 ++++++++++++++++++---------------
 docs/system/arm/emulation.rst  |   2 +
 target/arm/tcg/sme.decode      | 118 ++++++++++++++++-----
 6 files changed, 201 insertions(+), 111 deletions(-)

-- 
2.43.0