amd_iommu: Honor DTE[IR] and DTE[IW] when DTE[Mode] is 0

[PATCH 0/2] amd_iommu: Honor DTE[IR] and DTE[IW] when DTE[Mode] is 0

Daniel Paziyski posted 2 patches 6 days, 18 hours ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260718175208.118721-1-danielpaziyski@gmail.com

Maintainers: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>, Sairaj Kodilkar <sarunkod@amd.com>, Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, "Michael S. Tsirkin" <mst@redhat.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>

hw/i386/amd_iommu.c          | 136 ++++++++++++++-------
hw/i386/trace-events         |   2 +-
tests/qtest/amd-iommu-test.c | 230 +++++++++++++++++++++++++++++++++++
3 files changed, 322 insertions(+), 46 deletions(-)

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[PATCH 0/2] amd_iommu: Honor DTE[IR] and DTE[IW] when DTE[Mode] is 0

Posted by Daniel Paziyski 6 days, 18 hours ago

This patch implements honoring of the IR and IW bits, which determine whether
reads and writes are allowed, respectively, when passthrough mode (Mode = 0) is
enabled for a device.

A testcase is also provided, which tests different settings of these bits.
Moreover, I have tested that there are no problems with the existing page table
walking and IOTLB code, by running a virtual machine Arch Linux instance with
an AMD IOMMU and watching the trace_amdvi_translation_result tracepoint for the
storage device, and compiling QEMU and the test with UBSAN and ASAN.

Daniel Paziyski (2):
  amd_iommu: Honor DTE[IR] and DTE[IW] when DTE[Mode] is 0
  tests/qtest: Add amd-iommu passthrough mode test

 hw/i386/amd_iommu.c          | 136 ++++++++++++++-------
 hw/i386/trace-events         |   2 +-
 tests/qtest/amd-iommu-test.c | 230 +++++++++++++++++++++++++++++++++++
 3 files changed, 322 insertions(+), 46 deletions(-)

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2.55.0