Hi All,
This is v3 of the RFC adding named CPU model support for Arm64 in QEMU.
The main change in this revision is that the series is now rebased on top
of Eric Auger's "customizable host model" series [1], and adopts its
per-field SYSREG_<REG>_<FIELD>=<u64> property convention. v3 also scales
back a lot from v2 in terms of added "stuff", removing the concept of
"composites" and the support for exposing cache information to the guest.
Background:
=============================================================
Currently QEMU only supports -cpu host/max for KVM on Arm64. This blocks
live migration of VMs between hosts that differ in CPU features.
This RFC proposes hierarchical named models for Arm64 under KVM. A named
model is a strict contract of the CPU features exposed to the guest, so
the same model resolves to the same guest-visible ID registers on any
capable host. Models can be customized further by overriding individual
ID-register fields (e.g. SYSREG_ID_AA64ISAR0_EL1_SHA1=0).
On top of the models, this series adds the QMP introspection support on
Arm that the management layer already depends on for x86:
`query-cpu-definitions` lists the models a host can run and reports
blockers for the ones it cannot, `query-cpu-model-expansion` resolves a
model to its full set of properties, and the new `query-cpu-props-info`
reports the values the host supports for each property. The aim is feature
parity with x86 so existing tooling can consume Arm named models with
little change.
TL;DR examples:
=============================================================
# Boot a named model
qemu-system-aarch64 -cpu grace-v1 -machine virt,accel=kvm ...
# Named model with ID-register field override
qemu-system-aarch64 -cpu grace-v1,SYSREG_ID_AA64ISAR0_EL1_SHA1=0 ...
# -cpu host with ID-register field override
qemu-system-aarch64 -cpu host,SYSREG_ID_AA64ISAR0_EL1_AES=1 ...
# query-cpu-model-expansion
"model": {
"name": "graviton3-v1",
"props": {
"SYSREG_ID_AA64ISAR0_EL1_AES": 2,
"SYSREG_ID_AA64ISAR0_EL1_SHA1": 1,
"SYSREG_ID_AA64ISAR0_EL1_SHA2": 2,
"SYSREG_ID_AA64ISAR1_EL1_APA": 3,
"SYSREG_ID_AA64PFR0_EL1_SVE": 1,
"sve": true,
"sve128": true,
...
}
}
# query-cpu-definitions: blockers reporting
{
"name": "graviton3-v1",
"typename": "graviton3-v1-arm-cpu",
"unavailable-features": [
"SYSREG_ID_AA64MMFR0_EL1_TGran16_2",
"SYSREG_ID_AA64MMFR0_EL1_TGran64_2",
"SYSREG_ID_AA64MMFR0_EL1_TGran4_2",
"SYSREG_ID_AA64ISAR1_EL1_APA",
"SYSREG_ID_AA64ISAR0_EL1_SM3",
"SYSREG_ID_AA64ISAR0_EL1_SM4"
],
"static": false,
"deprecated": false
}
# new query-cpu-props-info: supported values per property
{
"name": "SYSREG_ID_AA64ISAR0_EL1_AES",
"supported-values": [
{ "min": 2, "max": 2 },
{ "min": 1, "max": 1 },
{ "min": 0, "max": 0 }
],
"type": "number"
},
{
"name": "sve",
"supported-values": [ true, false ],
"type": "boolean"
}
Planned Items for v4:
- Strict forward compatibility: Right now a model is only safe against a
newer host if QEMU happens to know the new ID registers. We can close
that gap: the fields we care about live in the Feature ID space
(ID_AA64PFR0_EL1 and friends), and the architecture already guarantees
unallocated encodings there RES0 - "Direct reads [...] behave
as Reserved, RES0 [...] if the encodings are used for ID registers in
the future" (DDI 0487M.a, D23.3). So any feature ID register that QEMU
does not know about must be "0" or enforced to "0" if writable by KVM.
- Special-case handling for CNTFRQ_EL0: make sure heterogeneous migration
does not happen between hosts with different CNTFRQ_EL0 values.
- Remove RESx properties.
- Both series struggle with how SYSREG_ properties interact with
already-defined QEMU properties like pauth/sve/pmu etc. We can solve
this by verifying that the cmdline property values match the
user-given values after we finalize the properties (something like
`enforce` in x86?).
Khushit Shah (18):
target/arm/sysreg: regenerate cpu-sysregs.h.inc
scripts: bug fixes in update-aarch64-cpu-sysreg-properties
target/arm: regenerate cpu-idregs.h.inc
target/arm: expose all ID regs fields as properties
target/arm/kvm: enable writable implementation ID registers
target/arm/kvm: Read all ID registers from KVM
target/arm/kvm: handle special ID registers cases when reading from
KVM
target/arm/kvm: Handle writeback for special ID register fields
target/arm: Add Nvidia Grace named model
target/arm: fix sve and pauth finalize for named cpu models
target/arm: Introduce stub files required for qmp support
target/arm/qmp: add named models and properties to cpu-model-expansion
target/arm/kvm: compute supported values for ID register fields
target/arm/kvm: introduce kvm_arm_get_host_isar helper
qmp: add query-cpu-props-info command
target/arm: Report 0 as supported for ID fields gated by vCPU init
flags
target/arm/qmp: hook blockers in query-cpu-definitions
target/arm/kvm: fix host model writeback when kernel supports EL2
Shaju Abraham (1):
target/arm: Add named cpu model infra + graviton3 named model
hw/arm/virt.c | 8 +
qapi/machine.json | 87 +++
.../update-aarch64-cpu-sysreg-properties.py | 67 ++-
stubs/meson.build | 1 +
stubs/qmp-cpu-props-info.c | 12 +
target/arm/arm-cpu-models-stub.c | 18 +
target/arm/arm-cpu-models.c | 533 +++++++++++++++++
target/arm/arm-cpu-models.h | 37 ++
target/arm/arm-qmp-cmds.c | 111 ++++
target/arm/cpu-idregs.c | 19 +
target/arm/cpu-idregs.h | 4 +
target/arm/cpu-idregs.h.inc | 165 +++---
target/arm/cpu-sysregs.h.inc | 1 +
target/arm/cpu64.c | 198 ++++++-
target/arm/internals.h | 6 +
target/arm/kvm-stub.c | 24 +-
target/arm/kvm.c | 560 ++++++++++++------
target/arm/kvm_arm.h | 52 +-
target/arm/meson.build | 8 +-
target/arm/trace-events | 6 +-
20 files changed, 1594 insertions(+), 323 deletions(-)
mode change 100644 => 100755 scripts/update-aarch64-cpu-sysreg-properties.py
create mode 100644 stubs/qmp-cpu-props-info.c
create mode 100644 target/arm/arm-cpu-models-stub.c
create mode 100644 target/arm/arm-cpu-models.c
create mode 100644 target/arm/arm-cpu-models.h
--
2.52.0