riscv: Add K230 DDR controller and PHY models

[PATCH 0/3] riscv: Add K230 DDR controller and PHY models

Junze Cao posted 3 patches 1 week, 2 days ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260716132423.931427-1-caojunze424@gmail.com

Maintainers: Chao Liu <chao.liu@processmission.com>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>

MAINTAINERS                 |   3 +
docs/system/riscv/k230.rst  |   4 +
hw/misc/k230_ddr.c          | 544 ++++++++++++++++++++++++++++++++++++
hw/misc/meson.build         |   1 +
hw/riscv/k230.c             |  19 +-
include/hw/misc/k230_ddr.h  |  59 ++++
include/hw/riscv/k230.h     |   4 +
tests/qtest/k230-ddr-test.c | 226 +++++++++++++++
tests/qtest/meson.build     |   3 +-
9 files changed, 859 insertions(+), 4 deletions(-)
create mode 100644 hw/misc/k230_ddr.c
create mode 100644 include/hw/misc/k230_ddr.h
create mode 100644 tests/qtest/k230-ddr-test.c

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[PATCH 0/3] riscv: Add K230 DDR controller and PHY models

Posted by Junze Cao 1 week, 2 days ago

The K230 SDK U-Boot SPL initializes DRAM by programming the DDRC CFG
and DDR PHY MMIO regions. The k230 machine currently exposes the DDR
configuration region as unimplemented and does not provide the PHY, so
the SPL cannot complete the training and DFI handshakes.

Add minimal models for the register behavior exercised by the SDK SPL.
The controller model provides reset values, register access policy, DFI
and software-update handshakes, and the Init-to-Normal transition. The
PHY model provides CSR ownership, the training mailbox, and DFI
completion. Wire both devices into the k230 machine and document the
resulting SPL support.

These device models allow firmware to complete the DDR initialization
sequence.

Testing performed:

* scripts/checkpatch.pl --branch upstream/master..HEAD
* meson test -C build --print-errorlogs
  qemu:qtest-riscv64/k230-ddr-test (6 subtests passed)
* Booted the K230 SDK U-Boot SPL through DDR initialization to its SPI
  boot path

Junze Cao (3):
  hw/misc: Add K230 DDR controller and PHY models
  hw/riscv: Connect K230 DDR controller and PHY models
  tests/qtest: Add K230 DDR controller tests

 MAINTAINERS                 |   3 +
 docs/system/riscv/k230.rst  |   4 +
 hw/misc/k230_ddr.c          | 544 ++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build         |   1 +
 hw/riscv/k230.c             |  19 +-
 include/hw/misc/k230_ddr.h  |  59 ++++
 include/hw/riscv/k230.h     |   4 +
 tests/qtest/k230-ddr-test.c | 226 +++++++++++++++
 tests/qtest/meson.build     |   3 +-
 9 files changed, 859 insertions(+), 4 deletions(-)
 create mode 100644 hw/misc/k230_ddr.c
 create mode 100644 include/hw/misc/k230_ddr.h
 create mode 100644 tests/qtest/k230-ddr-test.c


base-commit: eca2c16212ef9dcb0871de39bb9d1c2efebe76be
-- 
2.53.0