target/arm: Minor GICv5 cpuif bugfixes

[PATCH 0/2] target/arm: Minor GICv5 cpuif bugfixes

Peter Maydell posted 2 patches 1 week, 4 days ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260714091806.3568281-1-peter.maydell@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

target/arm/tcg/gicv5-cpuif.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

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[PATCH 0/2] target/arm: Minor GICv5 cpuif bugfixes

Posted by Peter Maydell 1 week, 4 days ago

This patchset is a couple of fixes for minor bugs in the GICv5
cpu interface code that I noticed while I was working on adding
virtualization support to it.

thanks
-- PMM

Peter Maydell (2):
  target/arm: GICv5 cpuif: gicr_cdia_read() ppibit should be 64 bits
  target/arm: GICv5 cpuif: Writes to ICC_APR_EL1 can change IRQ/FIQ

 target/arm/tcg/gicv5-cpuif.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH 1/2] target/arm: GICv5 cpuif: gicr_cdia_read() ppibit should be 64 bits
[PATCH 2/2] target/arm: GICv5 cpuif: Writes to ICC_APR_EL1 can change IRQ/FIQ