Hey all,

this is a follow up to a previous series "Add migration support to the
MSHV accelerator".

There were 2 contested changes that have been reworked in this series

- target/i386/mshv: migrate LAPIC state
- accel/mshv: introduce SaveVMHandler

"Introduce SaveVMHandler" was adding lifecycle hooks that froze the
timer at the start of the migration on the source, which effectively
paused any workload that would depend on timer progress (like an os)
during the migration window. This is undesired for live migration and
has been split out into a dedicated clock device that has its own
migration lifecycle in "hw/i386/mshv: migrate REFERENCE_TIME".

"Migrate LAPIC state" changed in 2 ways: 1) for mshv-specific fields
there is now an "MshvAPICState" object that captures auxiliary fields
that exist in the MSHV LAPIC state. Initially we also shadowed the
lvt[APIC_LVT_LINT0/1] fields, since a write to those fields was
triggering a userpace PIC delivery path that MSHV doesn't support.
2) We add a guard in "pic_irq_request()" to short-circuit the userland
delivery for MSHV for PIC interrupts, that means can use the LINT0/1
fields from the CommonAPICState.

The other migration steps have been carried over more or less
verbatim from the first patch series.

3 drive-by fixes:

- disable AMX TILE features: this is required on because we do not
  not support XSAVE buffers beyond 4k in the accelerator yet
- drop initial msi vector 0: this has produced a warning at launch,
  after tracing the source we can drop it silently with confidence.
- toggle fpu/xsave migration: a subtle bug where fpu state would be
  clobbered by xsave legacy space when applied in the wrong order.

best regards,

magnus

Magnus Kulke (12):
  target/i386/mshv: disable AMX TILE features
  accel/mshv: introduce SaveVMHandler
  hw/i386/mshv: migrate REFERENCE_TIME
  accel/mshv: install dummy handler for SIG_IPI
  target/i386/mshv: migrate LAPIC state
  target/i386/mshv: migrate Synic SINT MSRs
  target/i386/mshv: migrate SIMP and SIEFP state
  target/i386/mshv: migrate STIMER state
  accel/mshv: write synthetic MSRs after migration
  target/i386/mshv: migrate MP_STATE
  target/i386/mshv: toggle fpu/xsave migration
  hw/i386/mshv: drop initial msi vector 0

 MAINTAINERS                    |   1 +
 accel/mshv/mshv-all.c          |  98 ++++----
 accel/mshv/trace-events        |   1 +
 hw/i386/meson.build            |   1 +
 hw/i386/mshv/apic.c            | 405 +++++++++++++++++++++++++++++++++
 hw/i386/mshv/clock.c           | 189 +++++++++++++++
 hw/i386/mshv/meson.build       |   5 +
 hw/i386/x86-cpu.c              |   6 +
 include/hw/hyperv/hvgdk_mini.h |   5 +
 include/hw/i386/apic-msidef.h  |   1 +
 include/system/mshv.h          |   5 +
 include/system/mshv_int.h      |  19 +-
 target/i386/cpu-apic.c         |   3 +
 target/i386/cpu.h              |  10 +
 target/i386/machine.c          |  46 ++++
 target/i386/mshv/meson.build   |   1 +
 target/i386/mshv/mshv-cpu.c    | 305 +++++++++++++++++--------
 target/i386/mshv/msr.c         |  40 ++++
 target/i386/mshv/synic.c       | 206 +++++++++++++++++
 19 files changed, 1196 insertions(+), 151 deletions(-)
 create mode 100644 hw/i386/mshv/apic.c
 create mode 100644 hw/i386/mshv/clock.c
 create mode 100644 hw/i386/mshv/meson.build
 create mode 100644 target/i386/mshv/synic.c

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2.34.1