include/hw/arm/aspeed_ast1700.h | 2 +- include/hw/arm/aspeed_coprocessor.h | 11 ++- include/hw/arm/aspeed_soc.h | 1 + include/hw/misc/aspeed_scu.h | 5 ++ include/hw/ssi/aspeed_smc.h | 3 +- hw/arm/aspeed_ast27x0-fc.c | 38 +++++++--- hw/arm/aspeed_ast27x0-ssp.c | 56 +++++++++++--- hw/arm/aspeed_ast27x0-tsp.c | 56 +++++++++++--- hw/arm/aspeed_ast27x0.c | 16 ++-- hw/arm/aspeed_coprocessor_common.c | 2 - hw/misc/aspeed_scu.c | 20 ++++- hw/ssi/aspeed_smc.c | 113 ++++++++++++++++++++++++++-- 12 files changed, 267 insertions(+), 56 deletions(-)
The original AST2700 FC support series [1] is fairly large, making it
difficult to review all changes together.
To help speed up the review process, this series extracts the SCU/FMC-related
refactoring into a standalone prerequisite series.
v1:
Compared with the original series, the SCU preparation patch has been
split into three smaller patches:
Introduce Aspeed2700SCUState.
Convert AST1700/AST27x0 users to the new SCU subclass.
Move the SCU link property into the AST27x0-specific coprocessor
implementation.
In addition, the SCUIO reset handling has been separated into an
independent patch.
This series contains no functional changes. It is purely a refactoring
to isolate AST2700-specific SCU support from the generic implementation
and prepare for the subsequent AST2700 FC support.
v2:
1. Pass realized PSP SoC to SSP/TSP initialization
2. Share single SCUIO instance across PSP, SSP, and TSP
3. Share FMC controller with SSP and TSP
4. Add Data FIFO-based flash access support for
This series depends on:
https://patchwork.ozlabs.org/project/qemu-devel/cover/20260706052701.1141740-1-jamin_lin@aspeedtech.com/
Supersedes the following patches from the original FC support series [1]:
Patch 1:
https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-2-jamin_lin@aspeedtech.com/
Patch 2:
https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-3-jamin_lin@aspeedtech.com/
Patch 4:
https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-12-jamin_lin@aspeedtech.com/
Patch 15:
https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-16-jamin_lin@aspeedtech.com/
Patch 18:
https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-19-jamin_lin@aspeedtech.com/
Patch
[1] Original AST2700 FC support series:
https://patchwork.kernel.org/project/qemu-devel/cover/20260417032837.2664122-1-jamin_lin@aspeedtech.com/
Jamin Lin (8):
hw/misc/aspeed_scu: Introduce Aspeed2700SCUState
hw/arm/aspeed: Use Aspeed2700SCUState for AST2700 users
hw/arm/aspeed_ast27x0: Move SCU link into AST27x0 coprocessors
hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO
hw/arm/aspeed_ast27x0: Pass realized PSP SoC to SSP/TSP initialization
hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP
hw/arm/ast27x0: Share FMC controller with SSP and TSP
hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for
AST2700
include/hw/arm/aspeed_ast1700.h | 2 +-
include/hw/arm/aspeed_coprocessor.h | 11 ++-
include/hw/arm/aspeed_soc.h | 1 +
include/hw/misc/aspeed_scu.h | 5 ++
include/hw/ssi/aspeed_smc.h | 3 +-
hw/arm/aspeed_ast27x0-fc.c | 38 +++++++---
hw/arm/aspeed_ast27x0-ssp.c | 56 +++++++++++---
hw/arm/aspeed_ast27x0-tsp.c | 56 +++++++++++---
hw/arm/aspeed_ast27x0.c | 16 ++--
hw/arm/aspeed_coprocessor_common.c | 2 -
hw/misc/aspeed_scu.c | 20 ++++-
hw/ssi/aspeed_smc.c | 113 ++++++++++++++++++++++++++--
12 files changed, 267 insertions(+), 56 deletions(-)
--
2.43.0
Hi Jamin,
On 7/7/26 08:09, Jamin Lin wrote:
> The original AST2700 FC support series [1] is fairly large, making it
> difficult to review all changes together.
>
> To help speed up the review process, this series extracts the SCU/FMC-related
> refactoring into a standalone prerequisite series.
> Jamin Lin (8):
> hw/misc/aspeed_scu: Introduce Aspeed2700SCUState
> hw/arm/aspeed: Use Aspeed2700SCUState for AST2700 users
> hw/arm/aspeed_ast27x0: Move SCU link into AST27x0 coprocessors
> hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO
> hw/arm/aspeed_ast27x0: Pass realized PSP SoC to SSP/TSP initialization
> hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP
> hw/arm/ast27x0: Share FMC controller with SSP and TSP
> hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for
> AST2700
Looking at this machine in more detail, I think it would be
better modelled as:
struct Ast2700FcMachineState {
MachineState parent_obj;
MemoryRegion dram;
Aspeed2700SCUState scu;
Aspeed27x0SoCState psp;
MemoryRegion psp_memory;
MemoryRegion psp_bootrom;
Aspeed27x0CoprocessorState ssp;
Clock *ssp_sysclk;
MemoryRegion ssp_memory;
Aspeed27x0CoprocessorState tsp;
Clock *tsp_sysclk;
MemoryRegion tsp_memory;
};
- dram and scu are shared within psp/ssp/tsp
(ca35_dram renamed as generic dram)
(ca35_memory renamed as psp_memory)
(ca35_boot_rom renamed as psp_bootrom)
and:
struct Aspeed27x0SoCState {
AspeedSoCState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
AspeedINTCState intc[ASPEED_INTC_NUM];
AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
GICv3State gic;
MemoryRegion dram_empty;
Aspeed2700SCUState *scu;
};
- scu becomes a link property
struct Ast2700FcMachineState {
MachineState parent_obj;
MemoryRegion dram;
Aspeed2700SCUState scu;
Aspeed27x0SoCState psp;
MemoryRegion psp_memory;
MemoryRegion psp_bootrom;
Aspeed27x0CoprocessorState ssp;
Clock *ssp_sysclk;
MemoryRegion ssp_memory;
Aspeed27x0CoprocessorState tsp;
Clock *tsp_sysclk;
MemoryRegion tsp_memory;
};
My personal style preference being:
struct Ast2700FcMachineState {
MachineState parent_obj;
MemoryRegion dram;
Aspeed2700SCUState scu;
struct {
Aspeed27x0SoCState mpcore;
MemoryRegion memory;
MemoryRegion bootrom;
} psp;
struct {
Aspeed27x0CoprocessorState mcu;
Clock *sysclk;
MemoryRegion memory;
} ssp;
struct {
Aspeed27x0CoprocessorState mcu;
Clock *sysclk;
MemoryRegion memory;
} tsp;
};
Hi Philippe
> Looking at this machine in more detail, I think it would be better modelled as:
>
> struct Ast2700FcMachineState {
> MachineState parent_obj;
>
> MemoryRegion dram;
> Aspeed2700SCUState scu;
>
> Aspeed27x0SoCState psp;
> MemoryRegion psp_memory;
> MemoryRegion psp_bootrom;
>
> Aspeed27x0CoprocessorState ssp;
> Clock *ssp_sysclk;
> MemoryRegion ssp_memory;
>
> Aspeed27x0CoprocessorState tsp;
> Clock *tsp_sysclk;
> MemoryRegion tsp_memory;
> };
>
> - dram and scu are shared within psp/ssp/tsp
> (ca35_dram renamed as generic dram)
> (ca35_memory renamed as psp_memory)
> (ca35_boot_rom renamed as psp_bootrom)
>
> and:
>
> struct Aspeed27x0SoCState {
> AspeedSoCState parent;
>
> ARMCPU cpu[ASPEED_CPUS_NUM];
> AspeedINTCState intc[ASPEED_INTC_NUM];
> AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
> GICv3State gic;
> MemoryRegion dram_empty;
> Aspeed2700SCUState *scu;
> };
>
> - scu becomes a link property
>
> struct Ast2700FcMachineState {
> MachineState parent_obj;
>
> MemoryRegion dram;
> Aspeed2700SCUState scu;
>
> Aspeed27x0SoCState psp;
> MemoryRegion psp_memory;
> MemoryRegion psp_bootrom;
>
> Aspeed27x0CoprocessorState ssp;
> Clock *ssp_sysclk;
> MemoryRegion ssp_memory;
>
> Aspeed27x0CoprocessorState tsp;
> Clock *tsp_sysclk;
> MemoryRegion tsp_memory;
> };
>
> My personal style preference being:
>
> struct Ast2700FcMachineState {
> MachineState parent_obj;
>
> MemoryRegion dram;
> Aspeed2700SCUState scu;
>
> struct {
> Aspeed27x0SoCState mpcore;
> MemoryRegion memory;
> MemoryRegion bootrom;
> } psp;
>
> struct {
> Aspeed27x0CoprocessorState mcu;
> Clock *sysclk;
> MemoryRegion memory;
> } ssp;
>
> struct {
> Aspeed27x0CoprocessorState mcu;
> Clock *sysclk;
> MemoryRegion memory;
> } tsp;
> };
Thanks for the suggestion. I've reworked Ast2700FCState to match your preferred nested-struct style — psp/ssp/tsp are now grouped structs (mpcore/memory/bootrom for psp, mcu/sysclk/memory for ssp and tsp),
and ca35_dram is renamed to the generic dram as you suggested. Diff attached/inline below. Built and boot-tested both ast2700fc and ast2700a2-evb to confirm nothing regressed.
One part I couldn't do yet: making Aspeed27x0SoCState.scu a link property.
The blocker is hw-strap1/hw-strap2: they're property aliases created in instance_init(), pointing at the embedded scu. Both ast2700fc.c and hw/arm/aspeed.c set them right after object creation, before realize — but a link wouldn't be populated that early, so the alias would point at NULL.
hw/arm/aspeed.c isn't AST2700-specific — it's shared by every Aspeed BMC board. Fixing the timing there would touch all 24 of them (2400/2500/2600/1030/1040/2700 combined). "I do not prefer to change it to a link property."
Thanks,
Jamin
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 058cea42ed..417162bb02 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -34,18 +34,25 @@ static struct arm_boot_info ast2700fc_board_info = {
struct Ast2700FCState {
MachineState parent_obj;
- MemoryRegion ca35_memory;
- MemoryRegion ca35_dram;
- MemoryRegion ca35_boot_rom;
- MemoryRegion ssp_memory;
- MemoryRegion tsp_memory;
-
- Clock *ssp_sysclk;
- Clock *tsp_sysclk;
-
- Aspeed27x0SoCState ca35;
- Aspeed27x0CoprocessorState ssp;
- Aspeed27x0CoprocessorState tsp;
+ MemoryRegion dram;
+
+ struct {
+ Aspeed27x0SoCState mpcore;
+ MemoryRegion memory;
+ MemoryRegion bootrom;
+ } psp;
+
+ struct {
+ Aspeed27x0CoprocessorState mcu;
+ Clock *sysclk;
+ MemoryRegion memory;
+ } ssp;
+
+ struct {
+ Aspeed27x0CoprocessorState mcu;
+ Clock *sysclk;
+ MemoryRegion memory;
+ } tsp;
};
#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
@@ -67,23 +74,23 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
DeviceState *dev = NULL;
uint64_t rom_size;
- object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a2");
- soc = ASPEED_SOC(&s->ca35);
+ object_initialize_child(OBJECT(s), "ca35", &s->psp.mpcore, "ast2700-a2");
+ soc = ASPEED_SOC(&s->psp.mpcore);
sc = ASPEED_SOC_GET_CLASS(soc);
- memory_region_init(&s->ca35_memory, OBJECT(&s->ca35), "ca35-memory",
+ memory_region_init(&s->psp.memory, OBJECT(&s->psp.mpcore), "psp-memory",
UINT64_MAX);
- memory_region_add_subregion(get_system_memory(), 0, &s->ca35_memory);
+ memory_region_add_subregion(get_system_memory(), 0, &s->psp.memory);
- if (!memory_region_init_ram(&s->ca35_dram, OBJECT(&s->ca35), "ca35-dram",
+ if (!memory_region_init_ram(&s->dram, OBJECT(&s->psp.mpcore), "dram",
AST2700FC_BMC_RAM_SIZE, errp)) {
return false;
}
- object_property_set_link(OBJECT(&s->ca35), "memory",
- OBJECT(&s->ca35_memory), &error_abort);
- object_property_set_link(OBJECT(&s->ca35), "dram", OBJECT(&s->ca35_dram),
- &error_abort);
- object_property_set_int(OBJECT(&s->ca35), "ram-size",
+ object_property_set_link(OBJECT(&s->psp.mpcore), "memory",
+ OBJECT(&s->psp.memory), &error_abort);
+ object_property_set_link(OBJECT(&s->psp.mpcore), "dram",
+ OBJECT(&s->dram), &error_abort);
+ object_property_set_int(OBJECT(&s->psp.mpcore), "ram-size",
AST2700FC_BMC_RAM_SIZE, &error_abort);
for (int i = 0; i < sc->macs_num; i++) {
@@ -92,9 +99,9 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
break;
}
}
- object_property_set_int(OBJECT(&s->ca35), "hw-strap1",
+ object_property_set_int(OBJECT(&s->psp.mpcore), "hw-strap1",
AST2700FC_HW_STRAP1, &error_abort);
- object_property_set_int(OBJECT(&s->ca35), "hw-strap2",
+ object_property_set_int(OBJECT(&s->psp.mpcore), "hw-strap2",
AST2700FC_HW_STRAP2, &error_abort);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base,
sc->uarts_num, serial_hd(0));
@@ -102,7 +109,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(1));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
- if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
+ if (!qdev_realize(DEVICE(&s->psp.mpcore), NULL, errp)) {
return false;
}
@@ -122,7 +129,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
if (fmc0) {
rom_size = memory_region_size(&soc->spi_boot);
- aspeed_install_boot_rom(soc, fmc0, &s->ca35_boot_rom, rom_size);
+ aspeed_install_boot_rom(soc, fmc0, &s->psp.bootrom, rom_size);
}
/* VBOOTROM */
@@ -134,68 +141,68 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
return true;
}
-static bool ast2700fc_ssp_init(Ast2700FCState *s, AspeedSoCState *psp,
+static bool ast2700fc_ssp_init(Ast2700FCState *s, AspeedSoCState *soc,
Error **errp)
{
- s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
- clock_set_hz(s->ssp_sysclk, 200000000ULL);
+ s->ssp.sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
+ clock_set_hz(s->ssp.sysclk, 200000000ULL);
- object_initialize_child(OBJECT(s), "ssp", &s->ssp,
+ object_initialize_child(OBJECT(s), "ssp", &s->ssp.mcu,
TYPE_ASPEED27X0SSP_COPROCESSOR);
- memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory",
+ memory_region_init(&s->ssp.memory, OBJECT(&s->ssp.mcu), "ssp-memory",
UINT64_MAX);
- qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk);
- object_property_set_link(OBJECT(&s->ssp), "memory",
- OBJECT(&s->ssp_memory), &error_abort);
+ qdev_connect_clock_in(DEVICE(&s->ssp.mcu), "sysclk", s->ssp.sysclk);
+ object_property_set_link(OBJECT(&s->ssp.mcu), "memory",
+ OBJECT(&s->ssp.memory), &error_abort);
- object_property_set_link(OBJECT(&s->ssp), "uart",
- OBJECT(&psp->uart[4]), &error_abort);
- object_property_set_int(OBJECT(&s->ssp), "uart-dev", ASPEED_DEV_UART4,
+ object_property_set_link(OBJECT(&s->ssp.mcu), "uart",
+ OBJECT(&soc->uart[4]), &error_abort);
+ object_property_set_int(OBJECT(&s->ssp.mcu), "uart-dev", ASPEED_DEV_UART4,
&error_abort);
- object_property_set_link(OBJECT(&s->ssp), "sram",
- OBJECT(&psp->sram), &error_abort);
- object_property_set_link(OBJECT(&s->ssp), "scu",
- OBJECT(&s->ca35.scu), &error_abort);
- object_property_set_link(OBJECT(&s->ssp), "scuio",
- OBJECT(&psp->scuio), &error_abort);
- object_property_set_link(OBJECT(&s->ssp), "fmc",
- OBJECT(&psp->fmc), &error_abort);
- if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
+ object_property_set_link(OBJECT(&s->ssp.mcu), "sram",
+ OBJECT(&soc->sram), &error_abort);
+ object_property_set_link(OBJECT(&s->ssp.mcu), "scu",
+ OBJECT(&s->psp.mpcore.scu), &error_abort);
+ object_property_set_link(OBJECT(&s->ssp.mcu), "scuio",
+ OBJECT(&soc->scuio), &error_abort);
+ object_property_set_link(OBJECT(&s->ssp.mcu), "fmc",
+ OBJECT(&soc->fmc), &error_abort);
+ if (!qdev_realize(DEVICE(&s->ssp.mcu), NULL, errp)) {
return false;
}
return true;
}
-static bool ast2700fc_tsp_init(Ast2700FCState *s, AspeedSoCState *psp,
+static bool ast2700fc_tsp_init(Ast2700FCState *s, AspeedSoCState *soc,
Error **errp)
{
- s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
- clock_set_hz(s->tsp_sysclk, 200000000ULL);
+ s->tsp.sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
+ clock_set_hz(s->tsp.sysclk, 200000000ULL);
- object_initialize_child(OBJECT(s), "tsp", &s->tsp,
+ object_initialize_child(OBJECT(s), "tsp", &s->tsp.mcu,
TYPE_ASPEED27X0TSP_COPROCESSOR);
- memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory",
+ memory_region_init(&s->tsp.memory, OBJECT(&s->tsp.mcu), "tsp-memory",
UINT64_MAX);
- qdev_connect_clock_in(DEVICE(&s->tsp), "sysclk", s->tsp_sysclk);
- object_property_set_link(OBJECT(&s->tsp), "memory",
- OBJECT(&s->tsp_memory), &error_abort);
+ qdev_connect_clock_in(DEVICE(&s->tsp.mcu), "sysclk", s->tsp.sysclk);
+ object_property_set_link(OBJECT(&s->tsp.mcu), "memory",
+ OBJECT(&s->tsp.memory), &error_abort);
- object_property_set_link(OBJECT(&s->tsp), "uart",
- OBJECT(&psp->uart[7]), &error_abort);
- object_property_set_int(OBJECT(&s->tsp), "uart-dev", ASPEED_DEV_UART7,
+ object_property_set_link(OBJECT(&s->tsp.mcu), "uart",
+ OBJECT(&soc->uart[7]), &error_abort);
+ object_property_set_int(OBJECT(&s->tsp.mcu), "uart-dev", ASPEED_DEV_UART7,
&error_abort);
- object_property_set_link(OBJECT(&s->tsp), "sram",
- OBJECT(&psp->sram), &error_abort);
- object_property_set_link(OBJECT(&s->tsp), "scu",
- OBJECT(&s->ca35.scu), &error_abort);
- object_property_set_link(OBJECT(&s->tsp), "scuio",
- OBJECT(&psp->scuio), &error_abort);
- object_property_set_link(OBJECT(&s->tsp), "fmc",
- OBJECT(&psp->fmc), &error_abort);
- if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
+ object_property_set_link(OBJECT(&s->tsp.mcu), "sram",
+ OBJECT(&soc->sram), &error_abort);
+ object_property_set_link(OBJECT(&s->tsp.mcu), "scu",
+ OBJECT(&s->psp.mpcore.scu), &error_abort);
+ object_property_set_link(OBJECT(&s->tsp.mcu), "scuio",
+ OBJECT(&soc->scuio), &error_abort);
+ object_property_set_link(OBJECT(&s->tsp.mcu), "fmc",
+ OBJECT(&soc->fmc), &error_abort);
+ if (!qdev_realize(DEVICE(&s->tsp.mcu), NULL, errp)) {
return false;
}
@@ -214,7 +221,7 @@ static void ast2700fc_init(MachineState *machine)
* SRAM, SCU and SCUIO. Therefore the PSP SoC must be realized
* before the coprocessors are initialized.
*/
- psp = ASPEED_SOC(&s->ca35);
+ psp = ASPEED_SOC(&s->psp.mpcore);
ast2700fc_ssp_init(s, psp, &error_abort);
ast2700fc_tsp_init(s, psp, &error_abort);
}
On 7/16/26 08:22, Jamin Lin wrote:
> Hi Philippe
>
>> Looking at this machine in more detail, I think it would be better modelled as:
>>
>> struct Ast2700FcMachineState {
>> MachineState parent_obj;
>>
>> MemoryRegion dram;
>> Aspeed2700SCUState scu;
>>
>> Aspeed27x0SoCState psp;
>> MemoryRegion psp_memory;
>> MemoryRegion psp_bootrom;
>>
>> Aspeed27x0CoprocessorState ssp;
>> Clock *ssp_sysclk;
>> MemoryRegion ssp_memory;
>>
>> Aspeed27x0CoprocessorState tsp;
>> Clock *tsp_sysclk;
>> MemoryRegion tsp_memory;
>> };
>>
>> - dram and scu are shared within psp/ssp/tsp
>> (ca35_dram renamed as generic dram)
>> (ca35_memory renamed as psp_memory)
>> (ca35_boot_rom renamed as psp_bootrom)
>>
>> and:
>>
>> struct Aspeed27x0SoCState {
>> AspeedSoCState parent;
>>
>> ARMCPU cpu[ASPEED_CPUS_NUM];
>> AspeedINTCState intc[ASPEED_INTC_NUM];
>> AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
>> GICv3State gic;
>> MemoryRegion dram_empty;
>> Aspeed2700SCUState *scu;
>> };
>>
>> - scu becomes a link property
>>
>> struct Ast2700FcMachineState {
>> MachineState parent_obj;
>>
>> MemoryRegion dram;
>> Aspeed2700SCUState scu;
>>
>> Aspeed27x0SoCState psp;
>> MemoryRegion psp_memory;
>> MemoryRegion psp_bootrom;
>>
>> Aspeed27x0CoprocessorState ssp;
>> Clock *ssp_sysclk;
>> MemoryRegion ssp_memory;
>>
>> Aspeed27x0CoprocessorState tsp;
>> Clock *tsp_sysclk;
>> MemoryRegion tsp_memory;
>> };
>>
>> My personal style preference being:
>>
>> struct Ast2700FcMachineState {
>> MachineState parent_obj;
>>
>> MemoryRegion dram;
>> Aspeed2700SCUState scu;
>>
>> struct {
>> Aspeed27x0SoCState mpcore;
>> MemoryRegion memory;
>> MemoryRegion bootrom;
>> } psp;
>>
>> struct {
>> Aspeed27x0CoprocessorState mcu;
>> Clock *sysclk;
>> MemoryRegion memory;
>> } ssp;
>>
>> struct {
>> Aspeed27x0CoprocessorState mcu;
>> Clock *sysclk;
>> MemoryRegion memory;
>> } tsp;
>> };
>
> Thanks for the suggestion. I've reworked Ast2700FCState to match your preferred nested-struct style — psp/ssp/tsp are now grouped structs (mpcore/memory/bootrom for psp, mcu/sysclk/memory for ssp and tsp),
> and ca35_dram is renamed to the generic dram as you suggested. Diff attached/inline below. Built and boot-tested both ast2700fc and ast2700a2-evb to confirm nothing regressed.
>
> One part I couldn't do yet: making Aspeed27x0SoCState.scu a link property.
>
> The blocker is hw-strap1/hw-strap2: they're property aliases created in instance_init(), pointing at the embedded scu. Both ast2700fc.c and hw/arm/aspeed.c set them right after object creation, before realize — but a link wouldn't be populated that early, so the alias would point at NULL.
>
> hw/arm/aspeed.c isn't AST2700-specific — it's shared by every Aspeed BMC board. Fixing the timing there would touch all 24 of them (2400/2500/2600/1030/1040/2700 combined). "I do not prefer to change it to a link property."
>
> Thanks,
> Jamin
>
> diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
> index 058cea42ed..417162bb02 100644
> --- a/hw/arm/aspeed_ast27x0-fc.c
> +++ b/hw/arm/aspeed_ast27x0-fc.c
> @@ -34,18 +34,25 @@ static struct arm_boot_info ast2700fc_board_info = {
> struct Ast2700FCState {
> MachineState parent_obj;
>
> - MemoryRegion ca35_memory;
> - MemoryRegion ca35_dram;
> - MemoryRegion ca35_boot_rom;
> - MemoryRegion ssp_memory;
> - MemoryRegion tsp_memory;
> -
> - Clock *ssp_sysclk;
> - Clock *tsp_sysclk;
> -
> - Aspeed27x0SoCState ca35;
> - Aspeed27x0CoprocessorState ssp;
> - Aspeed27x0CoprocessorState tsp;
> + MemoryRegion dram;
> +
> + struct {
> + Aspeed27x0SoCState mpcore;
> + MemoryRegion memory;
> + MemoryRegion bootrom;
> + } psp;
> +
> + struct {
> + Aspeed27x0CoprocessorState mcu;
> + Clock *sysclk;
> + MemoryRegion memory;
> + } ssp;
> +
> + struct {
> + Aspeed27x0CoprocessorState mcu;
> + Clock *sysclk;
> + MemoryRegion memory;
> + } tsp;
I prefer the current version which reflects "a bit" better
the topology with the QOM tree. This is just personal test,
plus the intuition that Aspeed27x0CoprocessorState could
grow.
Thanks,
C.
On 7/7/26 08:09, Jamin Lin wrote: > The original AST2700 FC support series [1] is fairly large, making it > difficult to review all changes together. > > To help speed up the review process, this series extracts the SCU/FMC-related > refactoring into a standalone prerequisite series. > > v1: > Compared with the original series, the SCU preparation patch has been > split into three smaller patches: > > Introduce Aspeed2700SCUState. > Convert AST1700/AST27x0 users to the new SCU subclass. > Move the SCU link property into the AST27x0-specific coprocessor > implementation. > > In addition, the SCUIO reset handling has been separated into an > independent patch. > > This series contains no functional changes. It is purely a refactoring > to isolate AST2700-specific SCU support from the generic implementation > and prepare for the subsequent AST2700 FC support. > > v2: > 1. Pass realized PSP SoC to SSP/TSP initialization > 2. Share single SCUIO instance across PSP, SSP, and TSP > 3. Share FMC controller with SSP and TSP > 4. Add Data FIFO-based flash access support for > > This series depends on: > > https://patchwork.ozlabs.org/project/qemu-devel/cover/20260706052701.1141740-1-jamin_lin@aspeedtech.com/ > > Supersedes the following patches from the original FC support series [1]: > > Patch 1: > https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-2-jamin_lin@aspeedtech.com/ > > Patch 2: > https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-3-jamin_lin@aspeedtech.com/ > > Patch 4: > https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-12-jamin_lin@aspeedtech.com/ > > Patch 15: > https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-16-jamin_lin@aspeedtech.com/ > > Patch 18: > https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-19-jamin_lin@aspeedtech.com/ > > Patch > [1] Original AST2700 FC support series: > https://patchwork.kernel.org/project/qemu-devel/cover/20260417032837.2664122-1-jamin_lin@aspeedtech.com/ > > Jamin Lin (8): > hw/misc/aspeed_scu: Introduce Aspeed2700SCUState > hw/arm/aspeed: Use Aspeed2700SCUState for AST2700 users > hw/arm/aspeed_ast27x0: Move SCU link into AST27x0 coprocessors > hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO > hw/arm/aspeed_ast27x0: Pass realized PSP SoC to SSP/TSP initialization > hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP > hw/arm/ast27x0: Share FMC controller with SSP and TSP > hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for > AST2700 > > include/hw/arm/aspeed_ast1700.h | 2 +- > include/hw/arm/aspeed_coprocessor.h | 11 ++- > include/hw/arm/aspeed_soc.h | 1 + > include/hw/misc/aspeed_scu.h | 5 ++ > include/hw/ssi/aspeed_smc.h | 3 +- > hw/arm/aspeed_ast27x0-fc.c | 38 +++++++--- > hw/arm/aspeed_ast27x0-ssp.c | 56 +++++++++++--- > hw/arm/aspeed_ast27x0-tsp.c | 56 +++++++++++--- > hw/arm/aspeed_ast27x0.c | 16 ++-- > hw/arm/aspeed_coprocessor_common.c | 2 - > hw/misc/aspeed_scu.c | 20 ++++- > hw/ssi/aspeed_smc.c | 113 ++++++++++++++++++++++++++-- > 12 files changed, 267 insertions(+), 56 deletions(-) > Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C.
On 7/7/26 08:09, Jamin Lin wrote:
> The original AST2700 FC support series [1] is fairly large, making it
> difficult to review all changes together.
>
> To help speed up the review process, this series extracts the SCU/FMC-related
> refactoring into a standalone prerequisite series.
> hw/arm/aspeed_ast27x0-ssp.c | 56 +++++++++++---
> hw/arm/aspeed_ast27x0-tsp.c | 56 +++++++++++---
> hw/arm/aspeed_coprocessor_common.c | 2 -
It is unfortunate these 2 complex models diverge so few...
$ diff -u -U0 hw/arm/aspeed_ast27x0-tsp.c hw/arm/aspeed_ast27x0-ssp.c
--- hw/arm/aspeed_ast27x0-tsp.c 2026-07-09 18:42:33
+++ hw/arm/aspeed_ast27x0-ssp.c 2026-07-09 18:42:33
@@ -2 +2 @@
- * ASPEED Ast27x0 TSP Coprocessor
+ * ASPEED Ast27x0 SSP Coprocessor
@@ -19 +19 @@
-#define AST2700_TSP_SDRAM_SIZE (512 * MiB)
+#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
@@ -21 +21 @@
-static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
+static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
@@ -50 +50 @@
-static const int aspeed_soc_ast27x0tsp_irqmap[] = {
+static const int aspeed_soc_ast27x0ssp_irqmap[] = {
@@ -68,2 +68,2 @@
-/* TSPINT 164 */
-static const int ast2700_tsp164_intcmap[] = {
+/* SSPINT 164 */
+static const int ast2700_ssp164_intcmap[] = {
@@ -91 +91 @@
-static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
+static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
@@ -96 +96 @@
- {164, 1, 4, ast2700_tsp164_intcmap},
+ {164, 1, 4, ast2700_ssp164_intcmap},
@@ -104 +104 @@
-static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s,
+static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState *s,
@@ -107 +107 @@
- Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(s);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(s);
@@ -114,5 +114,5 @@
- for (i = 0; i < ARRAY_SIZE(ast2700_tsp_intcmap); i++) {
- if (sc->irqmap[dev] == ast2700_tsp_intcmap[i].irq) {
- assert(ast2700_tsp_intcmap[i].ptr);
- or_idx = ast2700_tsp_intcmap[i].orgate_idx;
- idx = ast2700_tsp_intcmap[i].intc_idx;
+ for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
+ assert(ast2700_ssp_intcmap[i].ptr);
+ or_idx = ast2700_ssp_intcmap[i].orgate_idx;
+ idx = ast2700_ssp_intcmap[i].intc_idx;
@@ -120 +120 @@
- ast2700_tsp_intcmap[i].ptr[dev]);
+ ast2700_ssp_intcmap[i].ptr[dev]);
@@ -127 +127 @@
-static void aspeed_soc_ast27x0tsp_init(Object *obj)
+static void aspeed_soc_ast27x0ssp_init(Object *obj)
@@ -129 +129 @@
- Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(obj);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(obj);
@@ -136 +136 @@
- TYPE_ASPEED_2700TSP_INTC);
+ TYPE_ASPEED_2700SSP_INTC);
@@ -138 +138 @@
- TYPE_ASPEED_2700TSP_INTCIO);
+ TYPE_ASPEED_2700SSP_INTCIO);
@@ -154 +154 @@
-static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error
**errp)
+static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error
**errp)
@@ -156 +156 @@
- Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(dev_soc);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(dev_soc);
@@ -170 +170 @@
- error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
+ error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
@@ -176 +176 @@
- error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
+ error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
@@ -182 +182 @@
- error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
+ error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
@@ -187 +187 @@
- /* AST27X0 TSP Core */
+ /* AST27X0 SSP Core */
@@ -196,2 +196,2 @@
- * The TSP starts in a powered-down state and can be powered up
- * by setting the TSP Control Register through the SCU
+ * The SSP starts in a powered-down state and can be powered up
+ * by setting the SSP Control Register through the SCU
@@ -208 +208 @@
- AST2700_TSP_SDRAM_SIZE, errp)) {
+ AST2700_SSP_SDRAM_SIZE, errp)) {
@@ -235,2 +235,5 @@
- /* SDRAM remap alias used by PSP to access TSP SDRAM */
- memory_region_add_subregion(&s->sdram, 0,
&a->scu->dram_remap_alias[2]);
+ /* SDRAM remap alias used by PSP to access SSP SDRAM */
+ memory_region_add_subregion(&s->sdram, 0,
&a->scu->dram_remap_alias[1]);
+ memory_region_add_subregion(&s->sdram,
+ memory_region_size(&a->scu->dram_remap_alias[1]),
+ &a->scu->dram_remap_alias[0]);
@@ -254 +257 @@
- /* irq source orgates -> INTC */
+ /* irq source orgates -> INTC0 */
@@ -260 +263 @@
- assert(i < ARRAY_SIZE(ast2700_tsp_intcmap));
+ assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
@@ -263 +266 @@
- ast2700_tsp_intcmap[i].irq));
+ ast2700_ssp_intcmap[i].irq));
@@ -265 +268 @@
- /* irq source orgates -> INTC */
+ /* irq source orgates -> INTCIO */
@@ -287 +290 @@
- aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
+ aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
@@ -325 +328 @@
-static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
+static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
@@ -329 +332 @@
- ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
@@ -337 +340 @@
- dc->realize = aspeed_soc_ast27x0tsp_realize;
+ dc->realize = aspeed_soc_ast27x0ssp_realize;
@@ -341,2 +344,2 @@
- sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
- sc->memmap = aspeed_soc_ast27x0tsp_memmap;
+ sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
+ sc->memmap = aspeed_soc_ast27x0ssp_memmap;
@@ -345 +348 @@
-static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
+static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
@@ -347 +350 @@
- .name = TYPE_ASPEED27X0TSP_COPROCESSOR,
+ .name = TYPE_ASPEED27X0SSP_COPROCESSOR,
@@ -350,2 +353,2 @@
- .instance_init = aspeed_soc_ast27x0tsp_init,
- .class_init = aspeed_soc_ast27x0tsp_class_init,
+ .instance_init = aspeed_soc_ast27x0ssp_init,
+ .class_init = aspeed_soc_ast27x0ssp_class_init,
@@ -355 +358 @@
-DEFINE_TYPES(aspeed_soc_ast27x0tsp_types)
+DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
And without the s/tsp/ssp/ name changes, the diff is as
small as:
$ diff -u -U0 hw/arm/aspeed_ast27x0-tsp.c hw/arm/aspeed_ast27x0-ssp.c
--- hw/arm/aspeed_ast27x0-tsp.c 2026-07-09 18:42:33
+++ hw/arm/aspeed_ast27x0-ssp.c 2026-07-10 01:10:06
@@ -236 +236,4 @@
- memory_region_add_subregion(&s->sdram, 0,
&a->scu->dram_remap_alias[2]);
+ memory_region_add_subregion(&s->sdram, 0,
&a->scu->dram_remap_alias[1]);
+ memory_region_add_subregion(&s->sdram,
+ memory_region_size(&a->scu->dram_remap_alias[1]),
+ &a->scu->dram_remap_alias[0]);
2 lines of differences! Could we unify?
Thanks,
Phil.
Hi Philippe, Cédric
> Subject: Re: [PATCH v2 0/8] Refactor AST2700 SCU preparation for coprocessors
>
> On 7/7/26 08:09, Jamin Lin wrote:
> > The original AST2700 FC support series [1] is fairly large, making it
> > difficult to review all changes together.
> >
> > To help speed up the review process, this series extracts the
> > SCU/FMC-related refactoring into a standalone prerequisite series.
>
>
> > hw/arm/aspeed_ast27x0-ssp.c | 56 +++++++++++---
> > hw/arm/aspeed_ast27x0-tsp.c | 56 +++++++++++---
> > hw/arm/aspeed_coprocessor_common.c | 2 -
>
> It is unfortunate these 2 complex models diverge so few...
>
> $ diff -u -U0 hw/arm/aspeed_ast27x0-tsp.c hw/arm/aspeed_ast27x0-ssp.c
> --- hw/arm/aspeed_ast27x0-tsp.c 2026-07-09 18:42:33
> +++ hw/arm/aspeed_ast27x0-ssp.c 2026-07-09 18:42:33
> @@ -2 +2 @@
> - * ASPEED Ast27x0 TSP Coprocessor
> + * ASPEED Ast27x0 SSP Coprocessor
> @@ -19 +19 @@
> -#define AST2700_TSP_SDRAM_SIZE (512 * MiB)
> +#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
> @@ -21 +21 @@
> -static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
> +static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> @@ -50 +50 @@
> -static const int aspeed_soc_ast27x0tsp_irqmap[] = {
> +static const int aspeed_soc_ast27x0ssp_irqmap[] = {
> @@ -68,2 +68,2 @@
> -/* TSPINT 164 */
> -static const int ast2700_tsp164_intcmap[] = {
> +/* SSPINT 164 */
> +static const int ast2700_ssp164_intcmap[] = {
> @@ -91 +91 @@
> -static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
> +static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
> @@ -96 +96 @@
> - {164, 1, 4, ast2700_tsp164_intcmap},
> + {164, 1, 4, ast2700_ssp164_intcmap},
> @@ -104 +104 @@
> -static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s,
> +static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState
> +*s,
> @@ -107 +107 @@
> - Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(s);
> + Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(s);
> @@ -114,5 +114,5 @@
> - for (i = 0; i < ARRAY_SIZE(ast2700_tsp_intcmap); i++) {
> - if (sc->irqmap[dev] == ast2700_tsp_intcmap[i].irq) {
> - assert(ast2700_tsp_intcmap[i].ptr);
> - or_idx = ast2700_tsp_intcmap[i].orgate_idx;
> - idx = ast2700_tsp_intcmap[i].intc_idx;
> + for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
> + if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
> + assert(ast2700_ssp_intcmap[i].ptr);
> + or_idx = ast2700_ssp_intcmap[i].orgate_idx;
> + idx = ast2700_ssp_intcmap[i].intc_idx;
> @@ -120 +120 @@
> - ast2700_tsp_intcmap[i].ptr[dev]);
> +
> ast2700_ssp_intcmap[i].ptr[dev]);
> @@ -127 +127 @@
> -static void aspeed_soc_ast27x0tsp_init(Object *obj)
> +static void aspeed_soc_ast27x0ssp_init(Object *obj)
> @@ -129 +129 @@
> - Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(obj);
> + Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(obj);
> @@ -136 +136 @@
> - TYPE_ASPEED_2700TSP_INTC);
> + TYPE_ASPEED_2700SSP_INTC);
> @@ -138 +138 @@
> - TYPE_ASPEED_2700TSP_INTCIO);
> + TYPE_ASPEED_2700SSP_INTCIO);
> @@ -154 +154 @@
> -static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error
> **errp)
> +static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error
> **errp)
> @@ -156 +156 @@
> - Aspeed27x0CoprocessorState *a =
> ASPEED27X0TSP_COPROCESSOR(dev_soc);
> + Aspeed27x0CoprocessorState *a =
> ASPEED27X0SSP_COPROCESSOR(dev_soc);
> @@ -170 +170 @@
> - error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
> + error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
> @@ -176 +176 @@
> - error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
> + error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
> @@ -182 +182 @@
> - error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
> + error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
> @@ -187 +187 @@
> - /* AST27X0 TSP Core */
> + /* AST27X0 SSP Core */
> @@ -196,2 +196,2 @@
> - * The TSP starts in a powered-down state and can be powered up
> - * by setting the TSP Control Register through the SCU
> + * The SSP starts in a powered-down state and can be powered up
> + * by setting the SSP Control Register through the SCU
> @@ -208 +208 @@
> - AST2700_TSP_SDRAM_SIZE, errp)) {
> + AST2700_SSP_SDRAM_SIZE, errp)) {
> @@ -235,2 +235,5 @@
> - /* SDRAM remap alias used by PSP to access TSP SDRAM */
> - memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[2]);
> + /* SDRAM remap alias used by PSP to access SSP SDRAM */
> + memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[1]);
> + memory_region_add_subregion(&s->sdram,
> + memory_region_size(&a->scu->dram_remap_alias[1]),
> + &a->scu->dram_remap_alias[0]);
> @@ -254 +257 @@
> - /* irq source orgates -> INTC */
> + /* irq source orgates -> INTC0 */
> @@ -260 +263 @@
> - assert(i < ARRAY_SIZE(ast2700_tsp_intcmap));
> + assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
> @@ -263 +266 @@
> -
> ast2700_tsp_intcmap[i].irq));
> +
> + ast2700_ssp_intcmap[i].irq));
> @@ -265 +268 @@
> - /* irq source orgates -> INTC */
> + /* irq source orgates -> INTCIO */
> @@ -287 +290 @@
> - aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
> + aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
> @@ -325 +328 @@
> -static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
> +static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
> @@ -329 +332 @@
> - ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
> + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
> @@ -337 +340 @@
> - dc->realize = aspeed_soc_ast27x0tsp_realize;
> + dc->realize = aspeed_soc_ast27x0ssp_realize;
> @@ -341,2 +344,2 @@
> - sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
> - sc->memmap = aspeed_soc_ast27x0tsp_memmap;
> + sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
> + sc->memmap = aspeed_soc_ast27x0ssp_memmap;
> @@ -345 +348 @@
> -static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
> +static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
> @@ -347 +350 @@
> - .name = TYPE_ASPEED27X0TSP_COPROCESSOR,
> + .name = TYPE_ASPEED27X0SSP_COPROCESSOR,
> @@ -350,2 +353,2 @@
> - .instance_init = aspeed_soc_ast27x0tsp_init,
> - .class_init = aspeed_soc_ast27x0tsp_class_init,
> + .instance_init = aspeed_soc_ast27x0ssp_init,
> + .class_init = aspeed_soc_ast27x0ssp_class_init,
> @@ -355 +358 @@
> -DEFINE_TYPES(aspeed_soc_ast27x0tsp_types)
> +DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
>
> And without the s/tsp/ssp/ name changes, the diff is as small as:
>
> $ diff -u -U0 hw/arm/aspeed_ast27x0-tsp.c hw/arm/aspeed_ast27x0-ssp.c
> --- hw/arm/aspeed_ast27x0-tsp.c 2026-07-09 18:42:33
> +++ hw/arm/aspeed_ast27x0-ssp.c 2026-07-10 01:10:06
> @@ -236 +236,4 @@
> - memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[2]);
> + memory_region_add_subregion(&s->sdram, 0,
> &a->scu->dram_remap_alias[1]);
> + memory_region_add_subregion(&s->sdram,
> + memory_region_size(&a->scu->dram_remap_alias[1]),
> + &a->scu->dram_remap_alias[0]);
>
> 2 lines of differences! Could we unify?
>
> Thanks,
>
> Phil.
Below is my initial revision — please evaluate whether it needs to be merged into a single .c file.
The SSP and TSP coprocessor files are now identical except for two things, both stemming from the fact that SSP and TSP share the same PSP SCU instance:
- INTC/INTCIO subtype (TYPE_ASPEED_2700SSP_INTC vs TYPE_ASPEED_2700TSP_INTC)
- DRAM remap alias wiring — the SCU owns a single dram_remap_alias[] array shared by both cores (SSP uses two entries, TSP uses one), so each coprocessor needs to know which slice belongs to it.
Thanks,
Jamin
/*
* ASPEED Ast27x0 SSP/TSP Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/core/qdev-clock.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_coprocessor.h"
#define AST2700_COPROCESSOR_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0_coprocessor_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_PRIC0] = 0x72140000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
[ASPEED_DEV_UART4] = 0x72C1A000,
[ASPEED_DEV_IPC0] = 0x72C1C000,
[ASPEED_DEV_FMC] = 0x74000000,
[ASPEED_DEV_PRIC1] = 0x74100000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
[ASPEED_DEV_OTP] = 0x74C07000,
[ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
[ASPEED_DEV_UART1] = 0x74C33100,
[ASPEED_DEV_UART2] = 0x74C33200,
[ASPEED_DEV_UART3] = 0x74C33300,
[ASPEED_DEV_UART5] = 0x74C33400,
[ASPEED_DEV_UART6] = 0x74C33500,
[ASPEED_DEV_UART7] = 0x74C33600,
[ASPEED_DEV_UART8] = 0x74C33700,
[ASPEED_DEV_UART9] = 0x74C33800,
[ASPEED_DEV_UART10] = 0x74C33900,
[ASPEED_DEV_UART11] = 0x74C33A00,
[ASPEED_DEV_UART12] = 0x74C33B00,
[ASPEED_DEV_IPC1] = 0x74C39000,
};
static const int aspeed_soc_ast27x0_coprocessor_irqmap[] = {
[ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_SCU] = 12,
[ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_UART0] = 164,
[ASPEED_DEV_UART1] = 164,
[ASPEED_DEV_UART2] = 164,
[ASPEED_DEV_UART3] = 164,
[ASPEED_DEV_UART5] = 164,
[ASPEED_DEV_UART6] = 164,
[ASPEED_DEV_UART7] = 164,
[ASPEED_DEV_UART8] = 164,
[ASPEED_DEV_UART9] = 164,
[ASPEED_DEV_UART10] = 164,
[ASPEED_DEV_UART11] = 164,
[ASPEED_DEV_UART12] = 164,
};
/* IRQ 164 fans out to per-UART interrupts inside the shared orgate */
static const int ast2700_coprocessor_164_intcmap[] = {
[ASPEED_DEV_UART0] = 7,
[ASPEED_DEV_UART1] = 8,
[ASPEED_DEV_UART2] = 9,
[ASPEED_DEV_UART3] = 10,
[ASPEED_DEV_UART5] = 11,
[ASPEED_DEV_UART6] = 12,
[ASPEED_DEV_UART7] = 13,
[ASPEED_DEV_UART8] = 14,
[ASPEED_DEV_UART9] = 15,
[ASPEED_DEV_UART10] = 16,
[ASPEED_DEV_UART11] = 17,
[ASPEED_DEV_UART12] = 18,
};
struct nvic_intc_irq_info {
int irq;
int intc_idx;
int orgate_idx;
const int *ptr;
};
static struct nvic_intc_irq_info ast2700_coprocessor_intcmap[] = {
{160, 1, 0, NULL},
{161, 1, 1, NULL},
{162, 1, 2, NULL},
{163, 1, 3, NULL},
{164, 1, 4, ast2700_coprocessor_164_intcmap},
{165, 1, 5, NULL},
{166, 1, 6, NULL},
{167, 1, 7, NULL},
{168, 1, 8, NULL},
{169, 1, 9, NULL},
};
static MemoryRegion *ast27x0ssp_dram_remap_alias(Aspeed2700SCUState *scu,
int *n)
{
*n = ARRAY_SIZE(scu->ssp_dram_remap_alias);
return scu->ssp_dram_remap_alias;
}
static MemoryRegion *ast27x0tsp_dram_remap_alias(Aspeed2700SCUState *scu,
int *n)
{
*n = ARRAY_SIZE(scu->tsp_dram_remap_alias);
return scu->tsp_dram_remap_alias;
}
static qemu_irq aspeed_soc_ast27x0_coprocessor_get_irq(AspeedCoprocessorState *s,
int dev)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0_COPROCESSOR(s);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
int idx;
int i;
for (i = 0; i < ARRAY_SIZE(ast2700_coprocessor_intcmap); i++) {
if (sc->irqmap[dev] == ast2700_coprocessor_intcmap[i].irq) {
assert(ast2700_coprocessor_intcmap[i].ptr);
or_idx = ast2700_coprocessor_intcmap[i].orgate_idx;
idx = ast2700_coprocessor_intcmap[i].intc_idx;
return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
ast2700_coprocessor_intcmap[i].ptr[dev]);
}
}
return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
}
static void aspeed_soc_ast27x0_coprocessor_init(Object *obj)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0_COPROCESSOR(obj);
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_GET_CLASS(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
object_initialize_child(obj, "intc0", &a->intc[0], c->intc_type);
object_initialize_child(obj, "intc1", &a->intc[1], c->intcio_type);
object_initialize_child(obj, "timerctrl", &s->timerctrl,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ipc0", &a->ipc[0],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ipc1", &a->ipc[1],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric0", &a->pric[0],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric1", &a->pric[1],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "otp", &a->otp,
TYPE_UNIMPLEMENTED_DEVICE);
}
static void aspeed_soc_ast27x0_coprocessor_realize(DeviceState *dev_soc,
Error **errp)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0_COPROCESSOR(dev_soc);
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_GET_CLASS(dev_soc);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
MemoryRegion *mr;
MemoryRegion *remaps;
g_autofree char *sdram_name = NULL;
hwaddr remap_off;
int n;
int i;
if (!clock_has_source(s->sysclk)) {
error_setg(errp, "sysclk clock must be wired up by the board code");
return;
}
if (!a->scu) {
error_setg(errp, "%s: 'scu' link is not set",
object_get_typename(OBJECT(dev_soc)));
return;
}
if (!a->scuio) {
error_setg(errp, "%s: 'scuio' link is not set",
object_get_typename(OBJECT(dev_soc)));
return;
}
if (!a->fmc) {
error_setg(errp, "%s: 'fmc' link is not set",
object_get_typename(OBJECT(dev_soc)));
return;
}
/* AST27X0 SSP/TSP Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
qdev_prop_set_string(armv7m, "cpu-type",
aspeed_soc_cpu_type(sc->valid_cpu_types));
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
/*
* The coprocessor starts in a powered-down state and can be powered up
* by setting its Control Register through the SCU (System Control Unit)
*/
object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
sdram_name = g_strdup_printf("aspeed.sdram.%d",
CPU(a->armv7m.cpu)->cpu_index);
if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
AST2700_COPROCESSOR_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SDRAM],
&s->sdram);
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
memory_region_init_alias(&a->scu_alias, OBJECT(a), "scu.alias",
&a->scu->parent_obj.iomem, 0,
memory_region_size(&a->scu->parent_obj.iomem));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&a->scu_alias);
/* SCUIO */
memory_region_init_alias(&a->scuio_alias, OBJECT(a), "scuio.alias",
&a->scuio->iomem, 0,
memory_region_size(&a->scuio->iomem));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
&a->scuio_alias);
/*
* SDRAM remap alias used by PSP to access this coprocessor's SDRAM.
* Which/how many dram_remap_alias entries to concatenate is a per-model
* detail (see Aspeed27x0CoprocessorClass): SSP maps two, TSP maps one.
*/
remaps = c->dram_remap_alias(a->scu, &n);
remap_off = 0;
for (i = 0; i < n; i++) {
memory_region_add_subregion(&s->sdram, remap_off, &remaps[i]);
remap_off += memory_region_size(&remaps[i]);
}
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC]);
/* INTCIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
return;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
sc->memmap[ASPEED_DEV_INTCIO]);
/* irq source orgates -> INTC0 */
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
}
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
assert(i < ARRAY_SIZE(ast2700_coprocessor_intcmap));
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
qdev_get_gpio_in(DEVICE(&a->armv7m),
ast2700_coprocessor_intcmap[i].irq));
}
/* irq source orgates -> INTCIO */
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
}
/* INTCIO -> INTC */
for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(s->uart), 0);
memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias", mr, 0,
memory_region_size(mr));
memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
&s->uart_alias);
/*
* Redirect the UART interrupt to the NVIC, replacing the default routing
* to the PSP's GIC.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
aspeed_soc_ast27x0_coprocessor_get_irq(s, s->uart_dev));
/* FMC */
memory_region_init_alias(&a->fmc_alias, OBJECT(a), "fmc.alias",
&a->fmc->mmio, 0,
memory_region_size(&a->fmc->mmio));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_FMC],
&a->fmc_alias);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]),
"aspeed.ipc0",
sc->memmap[ASPEED_DEV_IPC0], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
"aspeed.ipc1",
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
"aspeed.pric0",
sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
"aspeed.pric1",
sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->otp),
"aspeed.otp",
sc->memmap[ASPEED_DEV_OTP], 0x800);
}
static const Property aspeed_27x0_coprocessor_properties[] = {
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
DEFINE_PROP_LINK("scuio", Aspeed27x0CoprocessorState, scuio,
TYPE_ASPEED_SCU, AspeedSCUState *),
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
AspeedSMCState *),
};
static void aspeed_soc_ast27x0_coprocessor_class_init(ObjectClass *klass,
const void *data)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
NULL
};
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_CLASS(klass);
/* Reason: The Aspeed Coprocessor can only be instantiated from a board */
dc->user_creatable = false;
dc->realize = aspeed_soc_ast27x0_coprocessor_realize;
device_class_set_props(dc, aspeed_27x0_coprocessor_properties);
sc->valid_cpu_types = valid_cpu_types;
sc->irqmap = aspeed_soc_ast27x0_coprocessor_irqmap;
sc->memmap = aspeed_soc_ast27x0_coprocessor_memmap;
}
static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
const void *data)
{
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_CLASS(klass);
c->intc_type = TYPE_ASPEED_2700SSP_INTC;
c->intcio_type = TYPE_ASPEED_2700SSP_INTCIO;
c->dram_remap_alias = ast27x0ssp_dram_remap_alias;
}
static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
const void *data)
{
Aspeed27x0CoprocessorClass *c = ASPEED27X0_COPROCESSOR_CLASS(klass);
c->intc_type = TYPE_ASPEED_2700TSP_INTC;
c->intcio_type = TYPE_ASPEED_2700TSP_INTCIO;
c->dram_remap_alias = ast27x0tsp_dram_remap_alias;
}
static const TypeInfo aspeed_soc_ast27x0_coprocessor_types[] = {
{
.name = TYPE_ASPEED27X0_COPROCESSOR,
.parent = TYPE_ASPEED_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.class_size = sizeof(Aspeed27x0CoprocessorClass),
.instance_init = aspeed_soc_ast27x0_coprocessor_init,
.class_init = aspeed_soc_ast27x0_coprocessor_class_init,
.abstract = true,
},
{
.name = TYPE_ASPEED27X0SSP_COPROCESSOR,
.parent = TYPE_ASPEED27X0_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.class_init = aspeed_soc_ast27x0ssp_class_init,
},
{
.name = TYPE_ASPEED27X0TSP_COPROCESSOR,
.parent = TYPE_ASPEED27X0_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.class_init = aspeed_soc_ast27x0tsp_class_init,
},
};
DEFINE_TYPES(aspeed_soc_ast27x0_coprocessor_types)
aspeed_coprocessor.h
/*
* ASPEED Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ASPEED_COPROCESSOR_H
#define ASPEED_COPROCESSOR_H
#include "qom/object.h"
#include "hw/arm/aspeed_soc.h"
struct AspeedCoprocessorState {
DeviceState parent;
MemoryRegion *memory;
MemoryRegion sdram;
MemoryRegion *sram;
MemoryRegion sram_alias;
MemoryRegion uart_alias;
Clock *sysclk;
AspeedTimerCtrlState timerctrl;
SerialMM *uart;
int uart_dev;
};
#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
ASPEED_COPROCESSOR)
struct AspeedCoprocessorClass {
DeviceClass parent_class;
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
const hwaddr *memmap;
const int *irqmap;
};
struct Aspeed27x0CoprocessorState {
AspeedCoprocessorState parent;
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState pric[2];
UnimplementedDeviceState otp;
ARMv7MState armv7m;
MemoryRegion scu_alias;
MemoryRegion scuio_alias;
MemoryRegion fmc_alias;
Aspeed2700SCUState *scu;
AspeedSCUState *scuio;
AspeedSMCState *fmc;
};
/*
* TYPE_ASPEED27X0_COPROCESSOR is an abstract type shared by the SSP and TSP
* coprocessors: they use the exact same instance_init/realize logic and
* only differ in a handful of per-model constants (INTC subtype, and which
* SCU dram_remap_alias entries they map). Those constants live in
* Aspeed27x0CoprocessorClass and are set once by each concrete model's
* class_init (see aspeed_ast27x0-coprocessor.c). This is a reference/
* experimental merge of the former aspeed_ast27x0-ssp.c/-tsp.c, kept for
* comparison purposes.
*/
#define TYPE_ASPEED27X0_COPROCESSOR "aspeed27x0-coprocessor"
OBJECT_DECLARE_TYPE(Aspeed27x0CoprocessorState, Aspeed27x0CoprocessorClass,
ASPEED27X0_COPROCESSOR)
struct Aspeed27x0CoprocessorClass {
AspeedCoprocessorClass parent_class;
const char *intc_type;
const char *intcio_type;
/*
* Returns this coprocessor's own SCU dram-remap-alias array (already in
* the order it should be concatenated at this coprocessor's own SDRAM
* offset 0), and stores its length in *n.
*/
MemoryRegion *(*dram_remap_alias)(Aspeed2700SCUState *scu, int *n);
};
#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor"
#endif /* ASPEED_COPROCESSOR_H */
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 5c3f563dd5..8b747917d7 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c --- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -980,7 +980,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
case AST2700_SCU_SSP_CTRL_1:
case AST2700_SCU_SSP_CTRL_2:
mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
- &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ &a->ssp_dram_remap_alias[1] : &a->ssp_dram_remap_alias[0];
if (a->ssp_cpuid < 0 || mr == NULL) {
return;
}
@@ -993,7 +993,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
case AST2700_SCU_SSP_REMAP_ADDR_1:
case AST2700_SCU_SSP_REMAP_ADDR_2:
mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
- &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ &a->ssp_dram_remap_alias[1] : &a->ssp_dram_remap_alias[0];
if (a->ssp_cpuid < 0 || mr == NULL) {
return;
}
@@ -1005,7 +1005,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
case AST2700_SCU_SSP_REMAP_SIZE_1:
case AST2700_SCU_SSP_REMAP_SIZE_2:
mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
- &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ &a->ssp_dram_remap_alias[1] : &a->ssp_dram_remap_alias[0];
if (a->ssp_cpuid < 0 || mr == NULL) {
return;
}
@@ -1015,7 +1015,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
memory_region_transaction_commit();
break;
case AST2700_SCU_TSP_CTRL_1:
- mr = &a->dram_remap_alias[2];
+ mr = &a->tsp_dram_remap_alias[0];
if (a->tsp_cpuid < 0 || mr == NULL) {
return;
}
@@ -1026,7 +1026,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
memory_region_transaction_commit();
break;
case AST2700_SCU_TSP_REMAP_SIZE_2:
- mr = &a->dram_remap_alias[2];
+ mr = &a->tsp_dram_remap_alias[0];
if (a->tsp_cpuid < 0 || mr == NULL) {
return;
}
On 7/7/26 08:09, Jamin Lin wrote: > The original AST2700 FC support series [1] is fairly large, making it > difficult to review all changes together. > Jamin Lin (8): > hw/misc/aspeed_scu: Introduce Aspeed2700SCUState > hw/arm/aspeed: Use Aspeed2700SCUState for AST2700 users > hw/arm/aspeed_ast27x0: Move SCU link into AST27x0 coprocessors > hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO > hw/arm/aspeed_ast27x0: Pass realized PSP SoC to SSP/TSP initialization > hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP > hw/arm/ast27x0: Share FMC controller with SSP and TSP > hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for > AST2700 Series: Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
On 7/7/26 08:09, Jamin Lin wrote:
> The original AST2700 FC support series [1] is fairly large, making it
> difficult to review all changes together.
>
> To help speed up the review process, this series extracts the SCU/FMC-related
> refactoring into a standalone prerequisite series.
>
> v1:
> Compared with the original series, the SCU preparation patch has been
> split into three smaller patches:
>
> Introduce Aspeed2700SCUState.
> Convert AST1700/AST27x0 users to the new SCU subclass.
> Move the SCU link property into the AST27x0-specific coprocessor
> implementation.
>
> In addition, the SCUIO reset handling has been separated into an
> independent patch.
>
> This series contains no functional changes. It is purely a refactoring
> to isolate AST2700-specific SCU support from the generic implementation
> and prepare for the subsequent AST2700 FC support.
>
> v2:
> 1. Pass realized PSP SoC to SSP/TSP initialization
> 2. Share single SCUIO instance across PSP, SSP, and TSP
> 3. Share FMC controller with SSP and TSP
> 4. Add Data FIFO-based flash access support for
>
> This series depends on:
>
> https://patchwork.ozlabs.org/project/qemu-devel/cover/20260706052701.1141740-1-jamin_lin@aspeedtech.com/
>
> Supersedes the following patches from the original FC support series [1]:
>
> Patch 1:
> https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-2-jamin_lin@aspeedtech.com/
>
> Patch 2:
> https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-3-jamin_lin@aspeedtech.com/
>
> Patch 4:
> https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-12-jamin_lin@aspeedtech.com/
>
> Patch 15:
> https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-16-jamin_lin@aspeedtech.com/
>
> Patch 18:
> https://patchwork.kernel.org/project/qemu-devel/patch/20260417032837.2664122-19-jamin_lin@aspeedtech.com/
>
> Patch
> [1] Original AST2700 FC support series:
> https://patchwork.kernel.org/project/qemu-devel/cover/20260417032837.2664122-1-jamin_lin@aspeedtech.com/
>
> Jamin Lin (8):
> hw/misc/aspeed_scu: Introduce Aspeed2700SCUState
> hw/arm/aspeed: Use Aspeed2700SCUState for AST2700 users
> hw/arm/aspeed_ast27x0: Move SCU link into AST27x0 coprocessors
> hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO
> hw/arm/aspeed_ast27x0: Pass realized PSP SoC to SSP/TSP initialization
> hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP
> hw/arm/ast27x0: Share FMC controller with SSP and TSP
> hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for
> AST2700
>
> include/hw/arm/aspeed_ast1700.h | 2 +-
> include/hw/arm/aspeed_coprocessor.h | 11 ++-
> include/hw/arm/aspeed_soc.h | 1 +
> include/hw/misc/aspeed_scu.h | 5 ++
> include/hw/ssi/aspeed_smc.h | 3 +-
> hw/arm/aspeed_ast27x0-fc.c | 38 +++++++---
> hw/arm/aspeed_ast27x0-ssp.c | 56 +++++++++++---
> hw/arm/aspeed_ast27x0-tsp.c | 56 +++++++++++---
> hw/arm/aspeed_ast27x0.c | 16 ++--
> hw/arm/aspeed_coprocessor_common.c | 2 -
> hw/misc/aspeed_scu.c | 20 ++++-
> hw/ssi/aspeed_smc.c | 113 ++++++++++++++++++++++++++--
> 12 files changed, 267 insertions(+), 56 deletions(-)
>
Applied to
https://github.com/legoater/qemu aspeed-next
Thanks,
C.
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