hw/riscv/riscv-iommu: check DC.TC reserved bits

[PATCH] hw/riscv/riscv-iommu: check DC.TC reserved bits

Posted by Daniel Henrique Barboza 4 weeks ago

We are not checking for reserved TC bits being set during device context
validation.

Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3548
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 hw/riscv/riscv-iommu-bits.h | 3 +++
 hw/riscv/riscv-iommu.c      | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
index a938fd3eb4..f9b6f35170 100644
--- a/hw/riscv/riscv-iommu-bits.h
+++ b/hw/riscv/riscv-iommu-bits.h
@@ -308,6 +308,9 @@ struct riscv_iommu_dc {
 #define RISCV_IOMMU_DC_IOHGATP_GSCID    GENMASK_ULL(59, 44)
 #define RISCV_IOMMU_DC_IOHGATP_MODE     RISCV_IOMMU_ATP_MODE_FIELD
 
+#define RISCV_IOMMU_DC_TC_RESERVED      (GENMASK_ULL(23, 12) \
+                                         | GENMASK_ULL(63, 32))
+
 enum riscv_iommu_dc_iohgatp_modes {
     RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0,
     RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8,
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index c9687e01a8..c2c470b5df 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -752,6 +752,10 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMUState *s,
     uint32_t fsc_mode, msi_mode;
     uint64_t gatp;
 
+    if (ctx->tc & RISCV_IOMMU_DC_TC_RESERVED) {
+        return false;
+    }
+
     if (!(s->cap & RISCV_IOMMU_CAP_ATS) &&
         (ctx->tc & RISCV_IOMMU_DC_TC_EN_ATS ||
          ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI ||
-- 
2.43.0

Re: [PATCH] hw/riscv/riscv-iommu: check DC.TC reserved bits

Posted by Alistair Francis 3 weeks, 6 days ago

On Sun, Jun 28, 2026 at 5:48 AM Daniel Henrique Barboza
<daniel.barboza@oss.qualcomm.com> wrote:
>
> We are not checking for reserved TC bits being set during device context
> validation.
>
> Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3548
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  hw/riscv/riscv-iommu-bits.h | 3 +++
>  hw/riscv/riscv-iommu.c      | 4 ++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
> index a938fd3eb4..f9b6f35170 100644
> --- a/hw/riscv/riscv-iommu-bits.h
> +++ b/hw/riscv/riscv-iommu-bits.h
> @@ -308,6 +308,9 @@ struct riscv_iommu_dc {
>  #define RISCV_IOMMU_DC_IOHGATP_GSCID    GENMASK_ULL(59, 44)
>  #define RISCV_IOMMU_DC_IOHGATP_MODE     RISCV_IOMMU_ATP_MODE_FIELD
>
> +#define RISCV_IOMMU_DC_TC_RESERVED      (GENMASK_ULL(23, 12) \
> +                                         | GENMASK_ULL(63, 32))
> +
>  enum riscv_iommu_dc_iohgatp_modes {
>      RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0,
>      RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8,
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index c9687e01a8..c2c470b5df 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -752,6 +752,10 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMUState *s,
>      uint32_t fsc_mode, msi_mode;
>      uint64_t gatp;
>
> +    if (ctx->tc & RISCV_IOMMU_DC_TC_RESERVED) {
> +        return false;
> +    }
> +
>      if (!(s->cap & RISCV_IOMMU_CAP_ATS) &&
>          (ctx->tc & RISCV_IOMMU_DC_TC_EN_ATS ||
>           ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI ||
> --
> 2.43.0
>
>

Re: [PATCH] hw/riscv/riscv-iommu: check DC.TC reserved bits

Posted by Alistair Francis 3 weeks, 6 days ago

On Sun, Jun 28, 2026 at 5:48 AM Daniel Henrique Barboza
<daniel.barboza@oss.qualcomm.com> wrote:
>
> We are not checking for reserved TC bits being set during device context
> validation.
>
> Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3548
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/riscv-iommu-bits.h | 3 +++
>  hw/riscv/riscv-iommu.c      | 4 ++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
> index a938fd3eb4..f9b6f35170 100644
> --- a/hw/riscv/riscv-iommu-bits.h
> +++ b/hw/riscv/riscv-iommu-bits.h
> @@ -308,6 +308,9 @@ struct riscv_iommu_dc {
>  #define RISCV_IOMMU_DC_IOHGATP_GSCID    GENMASK_ULL(59, 44)
>  #define RISCV_IOMMU_DC_IOHGATP_MODE     RISCV_IOMMU_ATP_MODE_FIELD
>
> +#define RISCV_IOMMU_DC_TC_RESERVED      (GENMASK_ULL(23, 12) \
> +                                         | GENMASK_ULL(63, 32))
> +
>  enum riscv_iommu_dc_iohgatp_modes {
>      RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0,
>      RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8,
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index c9687e01a8..c2c470b5df 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -752,6 +752,10 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMUState *s,
>      uint32_t fsc_mode, msi_mode;
>      uint64_t gatp;
>
> +    if (ctx->tc & RISCV_IOMMU_DC_TC_RESERVED) {
> +        return false;
> +    }
> +
>      if (!(s->cap & RISCV_IOMMU_CAP_ATS) &&
>          (ctx->tc & RISCV_IOMMU_DC_TC_EN_ATS ||
>           ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI ||
> --
> 2.43.0
>
>