Another minor feature working toward SME2.2.

r~

Richard Henderson (10):
  target/arm: Enable FADD/FSUB (half-precision) with FEAT_SME_F8F16
  target/arm: Rename SME FMLAL/FMLSL patterns
  target/arm: Implement FMLAL (multiple, multiple and single, FP8 to
    FP16)
  target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16)
  target/arm: Implement FDOT (multiple, multiple and single, FP8 to
    FP16)
  target/arm: Implement DOT (multiple and indexed, FP8 to FP16)
  target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16)
  target/arm: Rename FVDOT pattern
  target/arm: Implement FVDOT (FP8 to FP16)
  target/arm: Enable FEAT_SME_F8F16 for -cpu max

 target/arm/cpu-features.h        | 11 +++++
 target/arm/tcg/helper-fp8-defs.h |  2 +
 linux-user/aarch64/elfload.c     |  1 +
 target/arm/tcg/cpu64.c           |  1 +
 target/arm/tcg/fp8_helper.c      | 58 +++++++++++++++++++++++++
 target/arm/tcg/translate-sme.c   | 72 +++++++++++++++++++++++---------
 docs/system/arm/emulation.rst    |  1 +
 target/arm/tcg/sme.decode        | 66 +++++++++++++++++++++--------
 8 files changed, 176 insertions(+), 36 deletions(-)

-- 
2.43.0

On Thu, 25 Jun 2026 at 02:52, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Another minor feature working toward SME2.2.
>
> r~
>
> Richard Henderson (10):
>   target/arm: Enable FADD/FSUB (half-precision) with FEAT_SME_F8F16
>   target/arm: Rename SME FMLAL/FMLSL patterns
>   target/arm: Implement FMLAL (multiple, multiple and single, FP8 to
>     FP16)
>   target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16)
>   target/arm: Implement FDOT (multiple, multiple and single, FP8 to
>     FP16)
>   target/arm: Implement DOT (multiple and indexed, FP8 to FP16)
>   target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16)
>   target/arm: Rename FVDOT pattern
>   target/arm: Implement FVDOT (FP8 to FP16)
>   target/arm: Enable FEAT_SME_F8F16 for -cpu max

If you agree with my suggested tweaks for patches 1, 6, 9,
I can take this into target-arm.next and adjust it there.
The only one that isn't totally obvious is the patch 9 one.

-- PMM

Richard Henderson <richard.henderson@linaro.org> writes:

> Another minor feature working toward SME2.2.

This conflicts heavily with master - did a bunch of stuff get merged
that broke it?

>
> r~
>
> Richard Henderson (10):
>   target/arm: Enable FADD/FSUB (half-precision) with FEAT_SME_F8F16
>   target/arm: Rename SME FMLAL/FMLSL patterns
>   target/arm: Implement FMLAL (multiple, multiple and single, FP8 to
>     FP16)
>   target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16)
>   target/arm: Implement FDOT (multiple, multiple and single, FP8 to
>     FP16)
>   target/arm: Implement DOT (multiple and indexed, FP8 to FP16)
>   target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16)
>   target/arm: Rename FVDOT pattern
>   target/arm: Implement FVDOT (FP8 to FP16)
>   target/arm: Enable FEAT_SME_F8F16 for -cpu max
>
>  target/arm/cpu-features.h        | 11 +++++
>  target/arm/tcg/helper-fp8-defs.h |  2 +
>  linux-user/aarch64/elfload.c     |  1 +
>  target/arm/tcg/cpu64.c           |  1 +
>  target/arm/tcg/fp8_helper.c      | 58 +++++++++++++++++++++++++
>  target/arm/tcg/translate-sme.c   | 72 +++++++++++++++++++++++---------
>  docs/system/arm/emulation.rst    |  1 +
>  target/arm/tcg/sme.decode        | 66 +++++++++++++++++++++--------
>  8 files changed, 176 insertions(+), 36 deletions(-)

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro

On Fri, 26 Jun 2026 at 11:07, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Richard Henderson <richard.henderson@linaro.org> writes:
>
> > Another minor feature working toward SME2.2.
>
> This conflicts heavily with master - did a bunch of stuff get merged
> that broke it?

It'll be based on the F8F32 series that's not yet upstream
(it's in my target-arm.next queue).

-- PMM

On Fri, 26 Jun 2026 at 11:16, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Fri, 26 Jun 2026 at 11:07, Alex Bennée <alex.bennee@linaro.org> wrote:
> >
> > Richard Henderson <richard.henderson@linaro.org> writes:
> >
> > > Another minor feature working toward SME2.2.
> >
> > This conflicts heavily with master - did a bunch of stuff get merged
> > that broke it?
>
> It'll be based on the F8F32 series that's not yet upstream
> (it's in my target-arm.next queue).


https://gitlab.com/pm215/qemu/-/commits/target-arm.next

including this series.

-- PMM