Add subsections for accel=on (nested Stage-1/Stage-2 translation) and
cmdqv (Tegra241 CMDQV hardware command queues) under "User-creatable
SMMUv3 devices".
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
docs/system/arm/virt.rst | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index f811e662d6..ae0be35d57 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -288,6 +288,32 @@ User-creatable SMMUv3 devices
-device pxb-pcie,id=pcie.1,numa_node=1
-device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1
+ *Accelerated SMMUv3 (nested translation)*
+
+ The ``accel=on`` option enables hardware-accelerated nested translation
+ for vfio-pci passthrough devices. In this mode the guest SMMU driver
+ programs its own Stage-1 page tables, with the host SMMUv3 handling both
+ Stage-1 (guest) and Stage-2 (host) translations in hardware. The host
+ SMMUv3 must support nested translation. This mode requires the iommufd
+ backend and is only supported when booting with ACPI (not device tree).
+
+ When ``accel=on``, QEMU automatically derives the values for the
+ ``ril``, ``ats``, ``oas``, ``ssidsize`` and ``cmdqv`` sub-options
+ from the host SMMUv3 capabilities unless they are set explicitly.
+
+ Example::
+
+ -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0,accel=on
+
+ *Accelerated SMMUv3 command queues (Tegra241 CMDQV)*
+
+ The ``cmdqv`` sub-option enables NVIDIA Tegra241 Command Queue
+ Virtualization (CMDQV) on supported hosts. With CMDQV, each accelerated
+ ``arm-smmuv3`` device gets dedicated hardware command queues and the
+ guest issues SMMU invalidation commands directly to real hardware,
+ bypassing QEMU and improving throughput for workloads that issue many
+ invalidations. Without it, every invalidation command traps into QEMU.
+
Linux guest kernel configuration
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2.43.0