[v3] target/arm: Add aarch64 GPC3 bypass windows

[PATCH v3 0/6] target/arm: Add aarch64 GPC3 bypass windows

Jim MacArthur posted 6 patches 1 month, 1 week ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260618-jmac-gpc3b-v3-0-353e546067e7@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

target/arm/cpu-features.h                 |   5 +
target/arm/cpu.h                          |   7 ++
target/arm/helper.c                       |  19 ++++
target/arm/ptw.c                          |  77 ++++++++++++++
target/arm/tcg/cpu64.c                    |   4 +-
tests/tcg/aarch64/Makefile.softmmu-target |  22 +++-
tests/tcg/aarch64/system/boot.S           |  65 ++++++++++++
tests/tcg/aarch64/system/boot.h           |  14 +++
tests/tcg/aarch64/system/gpc-test.c       | 165 ++++++++++++++++++++++++++++++
9 files changed, 371 insertions(+), 7 deletions(-)

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[PATCH v3 0/6] target/arm: Add aarch64 GPC3 bypass windows

Posted by Jim MacArthur 1 month, 1 week ago

Adds the GPC bypass windows defined in D9.2 of the Arm ARM. D9.8 (the 
APAS instruction) is not implemented yet.

A large part of this is testing. To test GPC effectively, we need to
check that memory accesses are causing exceptions, or not causing exceptions
as appropriate. For some tests, boot.S is altered to record certain
exceptions and continue executing the test. An alternative would be
to use gdbstub to break on locations inside the vector table and continue,
but this requires significant coordination between the C test binary and
Python test driver, so has been avoided for now.

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
Changes in v3:
- ptw.c: Simplified GPC address checks
- boot.S: Renamed 'ALT' to 'LOGGING' to better reflect its intended use,
  types and sizes for exported symbols
- A few formatting fixes
- Link to v2: https://lore.kernel.org/qemu-devel/20260603-jmac-gpc3b-v2-0-115c51936962@linaro.org

Changes in v2:
- ptw.c changes have been rewritten after a number of faults were found
- boot.S: Align exception_log to page
- target/arm/helper.c: flush all caches and remove redundant mask
- Switch on of GPC3 moved after feature implementation
- Link to v1: https://lore.kernel.org/qemu-devel/20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org

---
Jim MacArthur (6):
      target/arm/tcg/cpu64.c: Extra test for GPC3.
      target/arm: Setup new registers for GPC3
      target/arm/ptw.c: Add Granule Bypass Windows
      target/arm/cpu-features.h: x-rme now means GPC3
      tests/tcg/aarch64/system: Alternative boot object for exception logging
      tests/tcg/aarch64/system/gpc-test.c: Basic test for granule protection check

 target/arm/cpu-features.h                 |   5 +
 target/arm/cpu.h                          |   7 ++
 target/arm/helper.c                       |  19 ++++
 target/arm/ptw.c                          |  77 ++++++++++++++
 target/arm/tcg/cpu64.c                    |   4 +-
 tests/tcg/aarch64/Makefile.softmmu-target |  22 +++-
 tests/tcg/aarch64/system/boot.S           |  65 ++++++++++++
 tests/tcg/aarch64/system/boot.h           |  14 +++
 tests/tcg/aarch64/system/gpc-test.c       | 165 ++++++++++++++++++++++++++++++
 9 files changed, 371 insertions(+), 7 deletions(-)
---
base-commit: b0df6e2f2c6c45df8d4d286933799c623e124d98
change-id: 20260528-jmac-gpc3b-187f9d7cf0dd

Best regards,
-- 
Jim MacArthur <jim.macarthur@linaro.org>

Re: [PATCH v3 0/6] target/arm: Add aarch64 GPC3 bypass windows

Posted by Peter Maydell 1 month ago

On Thu, 18 Jun 2026 at 17:33, Jim MacArthur <jim.macarthur@linaro.org> wrote:
>
> Adds the GPC bypass windows defined in D9.2 of the Arm ARM. D9.8 (the
> APAS instruction) is not implemented yet.
>
> A large part of this is testing. To test GPC effectively, we need to
> check that memory accesses are causing exceptions, or not causing exceptions
> as appropriate. For some tests, boot.S is altered to record certain
> exceptions and continue executing the test. An alternative would be
> to use gdbstub to break on locations inside the vector table and continue,
> but this requires significant coordination between the C test binary and
> Python test driver, so has been avoided for now.
>
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>



Applied to target-arm.next, thanks.

-- PMM