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[PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec

Saif Abrar posted 9 patches 1 month, 1 week ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260617095058.652789-1-saif.abrar@linux.ibm.com
Maintainers: Nicholas Piggin <npiggin@gmail.com>, Aditya Gupta <adityag@linux.ibm.com>, Glenn Miles <milesg@linux.ibm.com>, Harsh Prateek Bora <harshpb@linux.ibm.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Gautam Menghani <gautam@linux.ibm.com>
hw/pci-host/pnv_phb.c               |   1 +
hw/pci-host/pnv_phb4.c              | 581 +++++++++++++++++++++++++---
include/hw/pci-host/pnv_phb4.h      |  16 +-
include/hw/pci-host/pnv_phb4_regs.h |  66 +++-
tests/qtest/meson.build             |   1 +
tests/qtest/pnv-host-i2c-test.c     |  13 +-
tests/qtest/pnv-phb-test.c          | 235 +++++++++++
tests/qtest/pnv-qtest-common.h      |  24 ++
tests/qtest/pnv-xive2-common.h      |   7 +-
9 files changed, 868 insertions(+), 76 deletions(-)
create mode 100644 tests/qtest/pnv-phb-test.c
create mode 100644 tests/qtest/pnv-qtest-common.h
[PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec
Posted by Saif Abrar 1 month, 1 week ago 
Hello,
This patchset resolves the review comments for v4:
https://lore.kernel.org/qemu-devel/20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com/

Thanks to all the reviewers for their efforts.

Major updates include the following:
- Rename to phb5.
- New file for common definitions used in tests/qtest/pnv-* files.
- Initializing PnvPHB4Class members within class_init method.
- Updated IODA3 PCT table max size to 128, each with 2 entries.
- Multiple general cleanups.

Tested with 'make check-qtest' , 'make check-functional-ppc64' and 'make check'.

Regards.

Saif Abrar (9):
  qtest/phb5: Add testbench for PHB
  pnv/phb5: Add reset logic to PHB5
  pnv/phb5: Implement sticky reset logic in PHB5
  pnv/phb5: Implement read-only and write-only bits of registers
  pnv/phb5: Implement write-clear and return 1's on unimplemented reg
    read
  pnv/phb5: Set link-active status in HPSTAT and LMR registers
  pnv/phb5: Set link speed and width in the DLP training control
    register
  pnv/phb5: Implement IODA PCT table
  pnv/phb5: Mask off LSI Source-ID based on number of interrupts

 hw/pci-host/pnv_phb.c               |   1 +
 hw/pci-host/pnv_phb4.c              | 581 +++++++++++++++++++++++++---
 include/hw/pci-host/pnv_phb4.h      |  16 +-
 include/hw/pci-host/pnv_phb4_regs.h |  66 +++-
 tests/qtest/meson.build             |   1 +
 tests/qtest/pnv-host-i2c-test.c     |  13 +-
 tests/qtest/pnv-phb-test.c          | 235 +++++++++++
 tests/qtest/pnv-qtest-common.h      |  24 ++
 tests/qtest/pnv-xive2-common.h      |   7 +-
 9 files changed, 868 insertions(+), 76 deletions(-)
 create mode 100644 tests/qtest/pnv-phb-test.c
 create mode 100644 tests/qtest/pnv-qtest-common.h

-- 
2.52.0
Re: [PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec
Posted by Saif Abrar 3 weeks, 5 days ago 
Hello Cedric, Michael,

Is it OK to retain you Rbs in the next v6?

or would you like to review this v5? (as the patches have evolved since 
you last reviewed.)

Regards,

Saif


On 17-06-2026 15:20, Saif Abrar wrote:
> Hello,
> This patchset resolves the review comments for v4:
> https://lore.kernel.org/qemu-devel/20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com/
>
> Thanks to all the reviewers for their efforts.
>
> Major updates include the following:
> - Rename to phb5.
> - New file for common definitions used in tests/qtest/pnv-* files.
> - Initializing PnvPHB4Class members within class_init method.
> - Updated IODA3 PCT table max size to 128, each with 2 entries.
> - Multiple general cleanups.
>
> Tested with 'make check-qtest' , 'make check-functional-ppc64' and 'make check'.
>
> Regards.
>
> Saif Abrar (9):
>    qtest/phb5: Add testbench for PHB
>    pnv/phb5: Add reset logic to PHB5
>    pnv/phb5: Implement sticky reset logic in PHB5
>    pnv/phb5: Implement read-only and write-only bits of registers
>    pnv/phb5: Implement write-clear and return 1's on unimplemented reg
>      read
>    pnv/phb5: Set link-active status in HPSTAT and LMR registers
>    pnv/phb5: Set link speed and width in the DLP training control
>      register
>    pnv/phb5: Implement IODA PCT table
>    pnv/phb5: Mask off LSI Source-ID based on number of interrupts
>
>   hw/pci-host/pnv_phb.c               |   1 +
>   hw/pci-host/pnv_phb4.c              | 581 +++++++++++++++++++++++++---
>   include/hw/pci-host/pnv_phb4.h      |  16 +-
>   include/hw/pci-host/pnv_phb4_regs.h |  66 +++-
>   tests/qtest/meson.build             |   1 +
>   tests/qtest/pnv-host-i2c-test.c     |  13 +-
>   tests/qtest/pnv-phb-test.c          | 235 +++++++++++
>   tests/qtest/pnv-qtest-common.h      |  24 ++
>   tests/qtest/pnv-xive2-common.h      |   7 +-
>   9 files changed, 868 insertions(+), 76 deletions(-)
>   create mode 100644 tests/qtest/pnv-phb-test.c
>   create mode 100644 tests/qtest/pnv-qtest-common.h
>
Re: [PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec
Posted by Cédric Le Goater 3 weeks, 4 days ago 
On 6/30/26 12:22, Saif Abrar wrote:
> Hello Cedric, Michael,
> 
> Is it OK to retain you Rbs in the next v6?

yes. I took a look.

Thanks,

C.


> 
> or would you like to review this v5? (as the patches have evolved since you last reviewed.)
> 
> Regards,
> 
> Saif
> 
> 
> On 17-06-2026 15:20, Saif Abrar wrote:
>> Hello,
>> This patchset resolves the review comments for v4:
>> https://lore.kernel.org/qemu-devel/20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com/
>>
>> Thanks to all the reviewers for their efforts.
>>
>> Major updates include the following:
>> - Rename to phb5.
>> - New file for common definitions used in tests/qtest/pnv-* files.
>> - Initializing PnvPHB4Class members within class_init method.
>> - Updated IODA3 PCT table max size to 128, each with 2 entries.
>> - Multiple general cleanups.
>>
>> Tested with 'make check-qtest' , 'make check-functional-ppc64' and 'make check'.
>>
>> Regards.
>>
>> Saif Abrar (9):
>>    qtest/phb5: Add testbench for PHB
>>    pnv/phb5: Add reset logic to PHB5
>>    pnv/phb5: Implement sticky reset logic in PHB5
>>    pnv/phb5: Implement read-only and write-only bits of registers
>>    pnv/phb5: Implement write-clear and return 1's on unimplemented reg
>>      read
>>    pnv/phb5: Set link-active status in HPSTAT and LMR registers
>>    pnv/phb5: Set link speed and width in the DLP training control
>>      register
>>    pnv/phb5: Implement IODA PCT table
>>    pnv/phb5: Mask off LSI Source-ID based on number of interrupts
>>
>>   hw/pci-host/pnv_phb.c               |   1 +
>>   hw/pci-host/pnv_phb4.c              | 581 +++++++++++++++++++++++++---
>>   include/hw/pci-host/pnv_phb4.h      |  16 +-
>>   include/hw/pci-host/pnv_phb4_regs.h |  66 +++-
>>   tests/qtest/meson.build             |   1 +
>>   tests/qtest/pnv-host-i2c-test.c     |  13 +-
>>   tests/qtest/pnv-phb-test.c          | 235 +++++++++++
>>   tests/qtest/pnv-qtest-common.h      |  24 ++
>>   tests/qtest/pnv-xive2-common.h      |   7 +-
>>   9 files changed, 868 insertions(+), 76 deletions(-)
>>   create mode 100644 tests/qtest/pnv-phb-test.c
>>   create mode 100644 tests/qtest/pnv-qtest-common.h
>>
Re: [PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec
Posted by Michael S. Tsirkin 3 weeks, 4 days ago 
On Tue, Jun 30, 2026 at 03:52:04PM +0530, Saif Abrar wrote:
> Hello Cedric, Michael,
> 
> Is it OK to retain you Rbs in the next v6?
> 
> or would you like to review this v5? (as the patches have evolved since you
> last reviewed.)
> 
> Regards,
> 
> Saif


I took a look again.

Reviewed-by: Michael S. Tsirkin <mst@redhat.com>

> On 17-06-2026 15:20, Saif Abrar wrote:
> > Hello,
> > This patchset resolves the review comments for v4:
> > https://lore.kernel.org/qemu-devel/20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com/
> > 
> > Thanks to all the reviewers for their efforts.
> > 
> > Major updates include the following:
> > - Rename to phb5.
> > - New file for common definitions used in tests/qtest/pnv-* files.
> > - Initializing PnvPHB4Class members within class_init method.
> > - Updated IODA3 PCT table max size to 128, each with 2 entries.
> > - Multiple general cleanups.
> > 
> > Tested with 'make check-qtest' , 'make check-functional-ppc64' and 'make check'.
> > 
> > Regards.
> > 
> > Saif Abrar (9):
> >    qtest/phb5: Add testbench for PHB
> >    pnv/phb5: Add reset logic to PHB5
> >    pnv/phb5: Implement sticky reset logic in PHB5
> >    pnv/phb5: Implement read-only and write-only bits of registers
> >    pnv/phb5: Implement write-clear and return 1's on unimplemented reg
> >      read
> >    pnv/phb5: Set link-active status in HPSTAT and LMR registers
> >    pnv/phb5: Set link speed and width in the DLP training control
> >      register
> >    pnv/phb5: Implement IODA PCT table
> >    pnv/phb5: Mask off LSI Source-ID based on number of interrupts
> > 
> >   hw/pci-host/pnv_phb.c               |   1 +
> >   hw/pci-host/pnv_phb4.c              | 581 +++++++++++++++++++++++++---
> >   include/hw/pci-host/pnv_phb4.h      |  16 +-
> >   include/hw/pci-host/pnv_phb4_regs.h |  66 +++-
> >   tests/qtest/meson.build             |   1 +
> >   tests/qtest/pnv-host-i2c-test.c     |  13 +-
> >   tests/qtest/pnv-phb-test.c          | 235 +++++++++++
> >   tests/qtest/pnv-qtest-common.h      |  24 ++
> >   tests/qtest/pnv-xive2-common.h      |   7 +-
> >   9 files changed, 868 insertions(+), 76 deletions(-)
> >   create mode 100644 tests/qtest/pnv-phb-test.c
> >   create mode 100644 tests/qtest/pnv-qtest-common.h
> >
Re: [PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec
Posted by Aditya Gupta 1 month ago 
On 26/06/17 04:50AM, Saif Abrar wrote:
> Hello,
> This patchset resolves the review comments for v4:
> https://lore.kernel.org/qemu-devel/20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com/
> 
> Thanks to all the reviewers for their efforts.
> 
> Major updates include the following:
> - Rename to phb5.
> - New file for common definitions used in tests/qtest/pnv-* files.
> - Initializing PnvPHB4Class members within class_init method.
> - Updated IODA3 PCT table max size to 128, each with 2 entries.
> - Multiple general cleanups.
> 
> Tested with 'make check-qtest' , 'make check-functional-ppc64' and 'make check'.

Please don't keep Rbs of people unless explicitly given by them, see:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#proper-use-of-reviewed-by-tags-can-aid-review

Generally two things:
1. Rbs are explicitly given (replied to your patch) by person reviewing
it. If they reply with Rb on your cover letter, saying it's for the
whole series, that Rb can be kept on all patches in the series
2. If you feel your patch has significant changes, generally Rbs are to
be removed. Reviewers will be happy to send the Rbs again. I will let
other reviewers respond if they disagree.

As suggested by Harsh, would be good to rebase it on top of PHB5 patch
from jishnu, will help keep PHB5 (P10) and PHB4 (P9) separate.

Will be going through the patches.

Thanks,
- Aditya G
Re: [PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec
Posted by Harsh Prateek Bora 1 month ago 

On 17/06/26 3:20 pm, Saif Abrar wrote:
> Hello,
> This patchset resolves the review comments for v4:
> https://lore.kernel.org/qemu-devel/20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com/
> 
> Thanks to all the reviewers for their efforts.
> 
> Major updates include the following:
> - Rename to phb5.
> - New file for common definitions used in tests/qtest/pnv-* files.
> - Initializing PnvPHB4Class members within class_init method.
> - Updated IODA3 PCT table max size to 128, each with 2 entries.
> - Multiple general cleanups.
> 
> Tested with 'make check-qtest' , 'make check-functional-ppc64' and 'make check'.

Thanks Saif for addressing the review comments from reviews on v4.
I see you have also included Rb (Reviewed-by) tags from folks who gave
review comments on v4, but (at least me) didn't give Rb explicitly after
seeing the review comments addressed. We should add Rb only once the
reviewer explicitly provides it.
Also, could you please rebase this patchset on top of below PHB 4/5
refactoring patch from Jishnu:
https://lore.kernel.org/qemu-devel/20260608093430.2729688-1-jishnuvw@linux.ibm.com/

While I do not have any additional major review comments, I will let
other reviewers provide any additional feedback or Rb as appropriate.

regards,
Harsh
> 
> Regards.
> 
> Saif Abrar (9):
>    qtest/phb5: Add testbench for PHB
>    pnv/phb5: Add reset logic to PHB5
>    pnv/phb5: Implement sticky reset logic in PHB5
>    pnv/phb5: Implement read-only and write-only bits of registers
>    pnv/phb5: Implement write-clear and return 1's on unimplemented reg
>      read
>    pnv/phb5: Set link-active status in HPSTAT and LMR registers
>    pnv/phb5: Set link speed and width in the DLP training control
>      register
>    pnv/phb5: Implement IODA PCT table
>    pnv/phb5: Mask off LSI Source-ID based on number of interrupts
> 
>   hw/pci-host/pnv_phb.c               |   1 +
>   hw/pci-host/pnv_phb4.c              | 581 +++++++++++++++++++++++++---
>   include/hw/pci-host/pnv_phb4.h      |  16 +-
>   include/hw/pci-host/pnv_phb4_regs.h |  66 +++-
>   tests/qtest/meson.build             |   1 +
>   tests/qtest/pnv-host-i2c-test.c     |  13 +-
>   tests/qtest/pnv-phb-test.c          | 235 +++++++++++
>   tests/qtest/pnv-qtest-common.h      |  24 ++
>   tests/qtest/pnv-xive2-common.h      |   7 +-
>   9 files changed, 868 insertions(+), 76 deletions(-)
>   create mode 100644 tests/qtest/pnv-phb-test.c
>   create mode 100644 tests/qtest/pnv-qtest-common.h
>

Patchew 2.1-devel-ea86937

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