Three locations in helper_{rd,wr}msr() had '/* XXX: exception? */' placeholders
that silently ignored accesses to reserved or unimplemented MSRs instead of
raising #GP(0) as required by the Intel SDM (Vol. 2D, order 334569):
- helper_wrmsr() default case after MCE bank range check
- helper_rdmsr() MSR_MTRRcap when CPUID_MTRR not set
- helper_rdmsr() default case after MCE bank range check
Replace the silent fallthroughs with raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()).
Signed-off-by: Anastasiy <molenoch@protonmail.com>
---
target/i386/tcg/system/misc_helper.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c
index bb79d4e..e559d8f 100644
--- a/target/i386/tcg/system/misc_helper.c
+++ b/target/i386/tcg/system/misc_helper.c
@@ -318,8 +318,7 @@ void helper_wrmsr(CPUX86State *env)
}
break;
}
- /* XXX: exception? */
- break;
+ goto error;
}
return;
error:
@@ -442,8 +441,7 @@ void helper_rdmsr(CPUX86State *env)
val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
MSR_MTRRcap_WC_SUPPORTED;
} else {
- /* XXX: exception? */
- val = 0;
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
}
break;
case MSR_MCG_CAP:
@@ -493,9 +491,7 @@ void helper_rdmsr(CPUX86State *env)
val = env->mce_banks[offset];
break;
}
- /* XXX: exception? */
- val = 0;
- break;
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
}
env->regs[R_EAX] = (uint32_t)(val);
env->regs[R_EDX] = (uint32_t)(val >> 32);
--
2.53.0