This is Part 1 of the hexagon system emulation (sysemu) patch series,
providing the foundational target infrastructure needed for full-system
emulation of the Qualcomm Hexagon DSP.

Changes since v7:
  - Rebased onto current staging branch
  - Split "Introduce hexagon TLB device" into two patches: "Declare
    hexagon TLB device interface" (Part 1) and "Add hexagon TLB device
    implementation" (Part 3), so that Part 1 carries only the header
    and Part 3 carries the implementation alongside the machine that
    wires it up
  - Combined "Add stubs for modify_ssr/get_exe_mode" and
    "Update TARGET_PAGE_BITS" into a single patch
  - Removed Make gen_exception_end_tb non-static patch; no longer
    needed after restructuring

Previous versions:
  v7: https://lore.kernel.org/qemu-devel/20260529215554.606133-1-brian.cain@oss.qualcomm.com/
  v6: https://lore.kernel.org/qemu-devel/20260401152657.314902-1-brian.cain@oss.qualcomm.com/
  v5: https://lore.kernel.org/qemu-devel/20260311034923.1044737-1-brian.cain@oss.qualcomm.com/
  v4: https://lore.kernel.org/qemu-devel/20260309144822.877695-1-brian.cain@oss.qualcomm.com/
  v3: https://lore.kernel.org/qemu-devel/20260227203627.932864-1-brian.cain@oss.qualcomm.com/
  v2: https://lore.kernel.org/qemu-devel/20250902034715.1947718-1-brian.cain@oss.qualcomm.com/
  v1: https://lore.kernel.org/qemu-devel/20250301052628.1011210-1-brian.cain@oss.qualcomm.com/

Brian Cain (36):
  docs: Add hexagon sysemu docs
  docs/system: Add hexagon CPU emulation
  target/hexagon: Fix badva reference, delete CAUSE
  target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof
  target/hexagon: Handle system/guest registers in gen_analyze_funcs.py
    and hex_common.py
  target/hexagon: Suppress unused-variable warnings for sysemu source
    regs
  target/hexagon: Switch to tag_ignore(), generate via
    get_{user,sys}_tags()
  target/hexagon: Add privilege check, use tag_ignore()
  target/hexagon: Add a placeholder fp exception
  target/hexagon: Add guest, system reg number defs
  target/hexagon: Add guest, system reg number state
  target/hexagon: Add TCG values for sreg, greg
  target/hexagon: Add guest/sys reg writes to DisasContext
  target/hexagon: Add imported macro, attr defs for sysemu
  target/hexagon: Add new macro definitions for sysemu
  target/hexagon: Add handlers for guest/sysreg r/w
  target/hexagon: Add placeholder greg/sreg r/w helpers
  target/hexagon: Add vmstate representation
  target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()
  target/hexagon: Define register fields for system regs
  target/hexagon: Implement do_raise_exception()
  target/hexagon: Add system reg insns
  target/hexagon: Add sysemu TCG overrides
  target/hexagon: Add implicit attributes to sysemu macros
  target/hexagon: Add TCG overrides for int handler insts
  target/hexagon: Add TCG overrides for thread ctl
  target/hexagon: Add TCG overrides for rte, nmi
  target/hexagon: Add sreg_{read,write} helpers
  target/hexagon: Add representation to count cycles
  target/hexagon: Add implementation of cycle counters
  target/hexagon: Add pcycle setting functionality
  target/hexagon: Add cpu modes, mmu indices, next_PC to state
  hw/hexagon: Declare hexagon TLB device interface
  target/hexagon: Update TARGET_PAGE_BITS, stubs for
    modify_ssr/get_exe_mode
  target/hexagon: Define f{S,G}ET_FIELD macros
  target/hexagon: Add hex_interrupts support

 MAINTAINERS                             |   3 +
 docs/devel/hexagon-sys.rst              | 112 ++++++++
 docs/devel/index-internals.rst          |   1 +
 docs/system/hexagon/cdsp.rst            |  12 +
 docs/system/hexagon/emulation.rst       |  15 +
 docs/system/target-hexagon.rst          | 103 +++++++
 docs/system/targets.rst                 |   1 +
 include/hw/hexagon/hexagon_tlb.h        |  46 +++
 target/hexagon/cpu-param.h              |   2 +-
 target/hexagon/cpu.h                    |  75 ++++-
 target/hexagon/cpu_bits.h               |  75 ++++-
 target/hexagon/cpu_helper.h             |  18 ++
 target/hexagon/gen_tcg.h                |   9 +
 target/hexagon/gen_tcg_sys.h            | 114 ++++++++
 target/hexagon/helper.h                 |  24 ++
 target/hexagon/hex_interrupts.h         |  15 +
 target/hexagon/hex_mmu.h                |  26 ++
 target/hexagon/hex_regs.h               | 117 ++++++++
 target/hexagon/internal.h               |  18 ++
 target/hexagon/macros.h                 |  35 ++-
 target/hexagon/sys_macros.h             | 243 ++++++++++++++++
 target/hexagon/translate.h              |  46 +++
 target/hexagon/attribs_def.h.inc        |  35 ++-
 target/hexagon/reg_fields_def.h.inc     |  96 +++++++
 linux-user/hexagon/cpu_loop.c           |  16 ++
 target/hexagon/arch.c                   |   5 +
 target/hexagon/cpu.c                    |  66 ++++-
 target/hexagon/cpu_helper.c             | 399 ++++++++++++++++++++++++++
 target/hexagon/genptr.c                 | 155 ++++++++++
 target/hexagon/hex_interrupts.c         | 371 ++++++++++++++++++++++++
 target/hexagon/hex_mmu.c                | 268 ++++++++++++++++++
 target/hexagon/machine.c                |  32 +++
 target/hexagon/op_helper.c              | 148 +++++++++-
 target/hexagon/translate.c              |  56 +++-
 target/hexagon/gen_analyze_funcs.py     |  14 +-
 target/hexagon/gen_helper_funcs.py      |  26 +-
 target/hexagon/gen_helper_protos.py     |  23 +-
 target/hexagon/gen_idef_parser_funcs.py |   2 +
 target/hexagon/gen_op_attribs.py        |   2 +-
 target/hexagon/gen_opcodes_def.py       |   5 +-
 target/hexagon/gen_tcg_funcs.py         |  35 ++-
 target/hexagon/hex_common.py            | 181 +++++++++++-
 target/hexagon/imported/encode_pp.def   | 128 ++++++++-
 target/hexagon/imported/macros.def      | 482 +++++++++++++++++++++++++++++++-
 target/hexagon/imported/system.idef     | 244 +++++++++++++++-
 target/hexagon/meson.build              |  13 +-
 46 files changed, 3801 insertions(+), 111 deletions(-)

--
2.34.1