Hi,

This is a follow-up to the series [0] that introduces support for
resolving 'auto' for arm-smmuv3 accelerated mode's ATS, RIL, SSIDSIZE,
and OAS feature properties based on host IOMMU capabilities. This is
dependent on the series [1] for changing these property types to accept
'auto' values.

Accelerated SMMUv3 Address Translation Services support is derived from
IDR0, Range Invalidation support is derived from IDR3, Substream ID
size is derived from IDR1, and output address space is derived from
IDR5.

The default values are set to 'auto' for all properties. If accel=off
and the values are set to 'auto' or are omitted and resolve to 'auto',
the default property values defined in smmuv3_init_id_regs() for OAS
and RIL will remain unchanged, while SSIDSIZE and ATS values will
remain initialized at 0.

A complete branch can be found here:
https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v6

Please take a look and let me know your feedback.

Thanks,
Nathan

[0] https://lore.kernel.org/all/20260605001712.1823737-1-nathanc@nvidia.com/
[1] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/

Changes from v5:
- Added R-by tags, thanks all!
- Rebase over latest upstream
  (https://lore.kernel.org/all/20260601215410.517009-15-stefanb@linux.ibm.com/)

Changes from v4:
- Added R-by tags, thanks all!
- Re-word smmuv3_class_init() accel description to list nested
  translation support as a pre-requisite
- Fix typo in smmuv3_class_init() SubstreamID size description

Changes from v3:
- Added R-by tags, thanks all!
- Include a fix patch for resolving ATS support in ATC invalidation
  case
- Update host requirements documented for accel=on, oas, and ssidsize
- Fix style issue, update comments
- Update function name for smmuv3_accel_machine_done
- Remove unnecessary early return for smmuv3_accel_machine_done
- Fix formatting in qemu-options.hx based on html render

Changes from v2:
- Added R-by tags, thanks Eric, Shameer, Cédric for the feedback!
- Re-worded descriptions in qemu-options.hx and smmu_validate_property()
- Emphasize accel=off auto behavior in a comment for smmuv3_properties[]

Changes from v1:
- Update qemu-options.hx to explicitly mention auto is supported
- Update qemu-options.hx to mention auto as default
- Simplify comments in smmuv3_accel_auto_finalise()
- Update descriptions in smmuv3_class_init()
- Consolidate all default value change patches into one patch
- Implement and use smmuv3_pasid_supported() for setting PASID support
  flag
- Move smmuv3_machine_done() and qemu_add_machine_init_done_notifier()
  to smmuv3-accel.c
- Register machine done notifier only in case auto_mode is set

Testing:
Basic sanity testing was performed on an NVIDIA Grace platform with GPU
device assignment and running CUDA test apps on the guest. Observed the
feature properties being set based on host IOMMU capabilities.
Verified that the VM boot will fail without a cold-plugged device, and
that a hot-plugged device re-uses the resolved values from the initial
cold-plug. Additional testing and feedback are welcome.

Nathan Chen (9):
  hw/arm/smmuv3: Update ATC invalidation check
  hw/arm/smmuv3: Improve accel SMMUv3 usage documentation
  hw/arm/smmuv3-accel: Add helper for resolving auto parameters
  hw/arm/smmuv3-accel: Implement "auto" value for "ats"
  hw/arm/smmuv3-accel: Implement "auto" value for "ril"
  hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize"
  hw/arm/smmuv3-accel: Implement "auto" value for "oas"
  hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto
  qemu-options.hx: Support "auto" for accel SMMUv3 properties

 hw/arm/smmuv3-accel.c   | 77 ++++++++++++++++++++++++++++++++++++++-
 hw/arm/smmuv3-accel.h   |  2 +
 hw/arm/smmuv3.c         | 81 +++++++++++++++++++++++------------------
 hw/core/machine.c       |  5 +++
 include/hw/arm/smmuv3.h |  3 ++
 qemu-options.hx         | 25 ++++++++++---
 6 files changed, 150 insertions(+), 43 deletions(-)

-- 
2.43.0

Hi Nathan, Peter,

On 6/8/26 7:48 PM, Nathan Chen wrote:
> Hi,
>
> This is a follow-up to the series [0] that introduces support for
> resolving 'auto' for arm-smmuv3 accelerated mode's ATS, RIL, SSIDSIZE,
> and OAS feature properties based on host IOMMU capabilities. This is
> dependent on the series [1] for changing these property types to accept
> 'auto' values.
>
> Accelerated SMMUv3 Address Translation Services support is derived from
> IDR0, Range Invalidation support is derived from IDR3, Substream ID
> size is derived from IDR1, and output address space is derived from
> IDR5.
>
> The default values are set to 'auto' for all properties. If accel=off
> and the values are set to 'auto' or are omitted and resolve to 'auto',
> the default property values defined in smmuv3_init_id_regs() for OAS
> and RIL will remain unchanged, while SSIDSIZE and ATS values will
> remain initialized at 0.
>
> A complete branch can be found here:
> https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v6
>
> Please take a look and let me know your feedback.

The series looks good to me and I tested it with Grace-Hopper GPU
passthrough
with explicit option settings and auto settings. It collected R-bs for
all the patches. Feel free to collect my T-b:

Tested-by: Eric Auger <eric.auger@redhat.com>

Peter, please could you consider pulling it if it suits you.  

There is also 
[PATCH v2] hw/pci/pci: Enforce pci_setup_iommu_per_bus() is called only
once per bus
which collected R-bs and does not clash with the above series

Thanks

Eric


>
> Thanks,
> Nathan
>
> [0] https://lore.kernel.org/all/20260605001712.1823737-1-nathanc@nvidia.com/
> [1] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/
>
> Changes from v5:
> - Added R-by tags, thanks all!
> - Rebase over latest upstream
>   (https://lore.kernel.org/all/20260601215410.517009-15-stefanb@linux.ibm.com/)
>
> Changes from v4:
> - Added R-by tags, thanks all!
> - Re-word smmuv3_class_init() accel description to list nested
>   translation support as a pre-requisite
> - Fix typo in smmuv3_class_init() SubstreamID size description
>
> Changes from v3:
> - Added R-by tags, thanks all!
> - Include a fix patch for resolving ATS support in ATC invalidation
>   case
> - Update host requirements documented for accel=on, oas, and ssidsize
> - Fix style issue, update comments
> - Update function name for smmuv3_accel_machine_done
> - Remove unnecessary early return for smmuv3_accel_machine_done
> - Fix formatting in qemu-options.hx based on html render
>
> Changes from v2:
> - Added R-by tags, thanks Eric, Shameer, Cédric for the feedback!
> - Re-worded descriptions in qemu-options.hx and smmu_validate_property()
> - Emphasize accel=off auto behavior in a comment for smmuv3_properties[]
>
> Changes from v1:
> - Update qemu-options.hx to explicitly mention auto is supported
> - Update qemu-options.hx to mention auto as default
> - Simplify comments in smmuv3_accel_auto_finalise()
> - Update descriptions in smmuv3_class_init()
> - Consolidate all default value change patches into one patch
> - Implement and use smmuv3_pasid_supported() for setting PASID support
>   flag
> - Move smmuv3_machine_done() and qemu_add_machine_init_done_notifier()
>   to smmuv3-accel.c
> - Register machine done notifier only in case auto_mode is set
>
> Testing:
> Basic sanity testing was performed on an NVIDIA Grace platform with GPU
> device assignment and running CUDA test apps on the guest. Observed the
> feature properties being set based on host IOMMU capabilities.
> Verified that the VM boot will fail without a cold-plugged device, and
> that a hot-plugged device re-uses the resolved values from the initial
> cold-plug. Additional testing and feedback are welcome.
>
> Nathan Chen (9):
>   hw/arm/smmuv3: Update ATC invalidation check
>   hw/arm/smmuv3: Improve accel SMMUv3 usage documentation
>   hw/arm/smmuv3-accel: Add helper for resolving auto parameters
>   hw/arm/smmuv3-accel: Implement "auto" value for "ats"
>   hw/arm/smmuv3-accel: Implement "auto" value for "ril"
>   hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize"
>   hw/arm/smmuv3-accel: Implement "auto" value for "oas"
>   hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto
>   qemu-options.hx: Support "auto" for accel SMMUv3 properties
>
>  hw/arm/smmuv3-accel.c   | 77 ++++++++++++++++++++++++++++++++++++++-
>  hw/arm/smmuv3-accel.h   |  2 +
>  hw/arm/smmuv3.c         | 81 +++++++++++++++++++++++------------------
>  hw/core/machine.c       |  5 +++
>  include/hw/arm/smmuv3.h |  3 ++
>  qemu-options.hx         | 25 ++++++++++---
>  6 files changed, 150 insertions(+), 43 deletions(-)
>

On Tue, 9 Jun 2026 at 08:49, Eric Auger <eric.auger@redhat.com> wrote:
>
> Hi Nathan, Peter,
>
> On 6/8/26 7:48 PM, Nathan Chen wrote:
> > Hi,
> >
> > This is a follow-up to the series [0] that introduces support for
> > resolving 'auto' for arm-smmuv3 accelerated mode's ATS, RIL, SSIDSIZE,
> > and OAS feature properties based on host IOMMU capabilities. This is
> > dependent on the series [1] for changing these property types to accept
> > 'auto' values.
> >
> > Accelerated SMMUv3 Address Translation Services support is derived from
> > IDR0, Range Invalidation support is derived from IDR3, Substream ID
> > size is derived from IDR1, and output address space is derived from
> > IDR5.
> >
> > The default values are set to 'auto' for all properties. If accel=off
> > and the values are set to 'auto' or are omitted and resolve to 'auto',
> > the default property values defined in smmuv3_init_id_regs() for OAS
> > and RIL will remain unchanged, while SSIDSIZE and ATS values will
> > remain initialized at 0.
> >
> > A complete branch can be found here:
> > https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v6
> >
> > Please take a look and let me know your feedback.
>
> The series looks good to me and I tested it with Grace-Hopper GPU
> passthrough
> with explicit option settings and auto settings. It collected R-bs for
> all the patches. Feel free to collect my T-b:
>
> Tested-by: Eric Auger <eric.auger@redhat.com>
>
> Peter, please could you consider pulling it if it suits you.

Thanks for taking on the testing and review for this -- I've
applied it to target-arm.next.

-- PMM