Hexagon sysemu part 2: runtime helpers -- interrupt delivery, TLB fill,
thread scheduling, MMU index, translation changes (pkt_ends_tb,
sreg/greg writes, COF decode), and physical memory access.

Changes in v5:
- ctx->pkt-> changed to ctx->pkt. throughout (upstream embedded the
  Packet struct).
- need_commit optimization in gen_sreg_writes(): skip t_sreg_new_value
  allocation when !need_commit && reg != SSR.
- Renamed "Add TLB, k0 {un,}lock" -> "Add k0 {un,}lock" (TLB setup
  is in Part 1 now).
- get_phys_page_debug -> get_phys_addr_debug (upstream rename).
- Format string fixes (%d/%x -> PRId32/PRIx32, uint32_t casts).
- Dropped Qualcomm manual citations from commit messages.
- Rebased onto current staging (cpu-interrupt.h, cpu.c class init
  context changes).

Patches still needing review:
- 03/28: target/hexagon: Implement start/stop helpers, soft reset
- 08/28: target/hexagon: Implement software interrupt
- 15/28: target/hexagon: Implement setprio, resched
- 21/28: target/hexagon: Add next_PC, {s,g}reg writes

Brian Cain (26):
  target/hexagon: Implement {c,}swi helpers
  target/hexagon: Implement iassign{r,w} helpers
  target/hexagon: Implement start/stop helpers, soft reset
  target/hexagon: Implement {g,s}etimask helpers
  target/hexagon: Implement wait helper
  target/hexagon: Implement get_exe_mode()
  target/hexagon: Implement hex_tlb_entry_get_perm()
  target/hexagon: Implement software interrupt
  target/hexagon: Implement stack overflow exception
  target/hexagon: Implement exec_interrupt, set_irq
  target/hexagon: Implement hexagon_tlb_fill()
  target/hexagon: Implement siad inst
  target/hexagon: Implement hexagon_resume_threads()
  target/hexagon: Implement setprio, resched
  target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()
  target/hexagon: extend hexagon_cpu_mmu_index() for sysemu
  target/hexagon: Decode trap1, rte as COF
  target/hexagon: Implement modify_ssr, resched, pending_interrupt
  target/hexagon: Add pkt_ends_tb to translation
  target/hexagon: Add next_PC, {s,g}reg writes
  target/hexagon: Add implicit sysreg writes
  target/hexagon: Define system, guest reg names
  target/hexagon: Add k0 {un,}lock
  target/hexagon: Add PC to raise_exception, use fTRAP() helper
  target/hexagon: Add TCG overrides for transfer insts
  target/hexagon: Add support for loadw_phys

Matheus Tavares Bernardino (2):
  target/hexagon: add simple cpu_exec_reset and pointer_wrap
  target/hexagon: Add guest reg reading functionality

 target/hexagon/cpu.h                        |  11 +
 target/hexagon/cpu_helper.h                 |   8 +
 target/hexagon/gen_tcg.h                    |   7 -
 target/hexagon/gen_tcg_sys.h                |  27 +-
 target/hexagon/helper.h                     |   6 +-
 target/hexagon/hexswi.h                     |  17 +
 target/hexagon/idef-parser/parser-helpers.h |   2 +
 target/hexagon/internal.h                   |   4 +
 target/hexagon/macros.h                     |   3 -
 target/hexagon/sys_macros.h                 |   7 +
 target/hexagon/translate.h                  |   5 +-
 target/hexagon/reg_fields_def.h.inc         |  11 +
 linux-user/hexagon/cpu_loop.c               |   7 +
 target/hexagon/cpu.c                        | 360 ++++++++++++++-
 target/hexagon/decode.c                     |  14 +
 target/hexagon/genptr.c                     |  18 +-
 target/hexagon/hex_mmu.c                    |   4 +-
 target/hexagon/hexswi.c                     | 270 ++++++++++++
 target/hexagon/idef-parser/parser-helpers.c |   9 +
 target/hexagon/op_helper.c                  | 462 +++++++++++++++++++-
 target/hexagon/translate.c                  | 216 ++++++++-
 target/hexagon/hex_common.py                |   3 +
 target/hexagon/idef-parser/idef-parser.y    |   3 +
 target/hexagon/imported/encode_pp.def       |   1 +
 target/hexagon/imported/ldst.idef           |   3 +
 25 files changed, 1422 insertions(+), 56 deletions(-)
 create mode 100644 target/hexagon/hexswi.h
 create mode 100644 target/hexagon/hexswi.c

-- 
2.34.1