Hexagon sysemu part 1: docs, system/guest register plumbing, TCG
overrides for privileged insns, cycle counters, MMU index, TLB device
interface, and interrupt support.
Changes in v7:
- Split "Introduce hexagon TLB device" into two commits: "Declare
hexagon TLB device interface" (header only) and "Define MMU_INDEX
TB_FLAGS field". TLB device implementation moved to Part 3.
- need_commit optimization in gen_log_sreg_write() and crswap
overrides: skip staging in t_sreg_new_value[] when !need_commit.
- hex_interrupts: dropped globalregs null-check ternaries (pointer
is always set); added exec-start-addr and global-regs properties.
- Picked up R-b from Pierrick on patches 15, 23.
- Rebased onto current staging (cpu-defs.h -> target_long.h, etc.).
- Format string fixes (%d/%x -> PRIx32/PRIu32).
Patches still needing review:
- 35/38: target/hexagon: Define MMU_INDEX TB_FLAGS field
- 36/38: target/hexagon: Add stubs for modify_ssr/get_exe_mode
- 38/38: target/hexagon: Add hex_interrupts support
Brian Cain (38):
docs: Add hexagon sysemu docs
docs/system: Add hexagon CPU emulation
target/hexagon: Fix badva reference, delete CAUSE
target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof
target/hexagon: Handle system/guest registers in gen_analyze_funcs.py
and hex_common.py
target/hexagon: Suppress unused-variable warnings for sysemu source
regs
target/hexagon: Make gen_exception_end_tb non-static
target/hexagon: Switch to tag_ignore(), generate via
get_{user,sys}_tags()
target/hexagon: Add privilege check, use tag_ignore()
target/hexagon: Add a placeholder fp exception
target/hexagon: Add guest, system reg number defs
target/hexagon: Add guest, system reg number state
target/hexagon: Add TCG values for sreg, greg
target/hexagon: Add guest/sys reg writes to DisasContext
target/hexagon: Add imported macro, attr defs for sysemu
target/hexagon: Add new macro definitions for sysemu
target/hexagon: Add handlers for guest/sysreg r/w
target/hexagon: Add placeholder greg/sreg r/w helpers
target/hexagon: Add vmstate representation
target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()
target/hexagon: Define register fields for system regs
target/hexagon: Implement do_raise_exception()
target/hexagon: Add system reg insns
target/hexagon: Add sysemu TCG overrides
target/hexagon: Add implicit attributes to sysemu macros
target/hexagon: Add TCG overrides for int handler insts
target/hexagon: Add TCG overrides for thread ctl
target/hexagon: Add TCG overrides for rte, nmi
target/hexagon: Add sreg_{read,write} helpers
target/hexagon: Add representation to count cycles
target/hexagon: Add implementation of cycle counters
target/hexagon: Add pcycle setting functionality
target/hexagon: Add cpu modes, mmu indices, next_PC to state
hw/hexagon: Declare hexagon TLB device interface
target/hexagon: Define MMU_INDEX TB_FLAGS field
target/hexagon: Add stubs for modify_ssr/get_exe_mode
target/hexagon: Define f{S,G}ET_FIELD macros
target/hexagon: Add hex_interrupts support
MAINTAINERS | 3 +
docs/devel/hexagon-sys.rst | 112 ++++++
docs/devel/index-internals.rst | 1 +
docs/system/hexagon/cdsp.rst | 12 +
docs/system/hexagon/emulation.rst | 15 +
docs/system/target-hexagon.rst | 103 +++++
docs/system/targets.rst | 1 +
include/hw/hexagon/hexagon_tlb.h | 46 +++
target/hexagon/cpu-param.h | 4 +
target/hexagon/cpu.h | 77 +++-
target/hexagon/cpu_bits.h | 75 +++-
target/hexagon/cpu_helper.h | 18 +
target/hexagon/gen_tcg.h | 9 +
target/hexagon/gen_tcg_sys.h | 117 ++++++
target/hexagon/helper.h | 22 ++
target/hexagon/hex_interrupts.h | 15 +
target/hexagon/hex_mmu.h | 26 ++
target/hexagon/hex_regs.h | 117 ++++++
target/hexagon/internal.h | 18 +
target/hexagon/macros.h | 35 +-
target/hexagon/sys_macros.h | 240 ++++++++++++
target/hexagon/translate.h | 46 +++
target/hexagon/attribs_def.h.inc | 35 +-
target/hexagon/reg_fields_def.h.inc | 96 +++++
linux-user/hexagon/cpu_loop.c | 16 +
target/hexagon/arch.c | 5 +
target/hexagon/cpu.c | 66 +++-
target/hexagon/cpu_helper.c | 399 ++++++++++++++++++++
target/hexagon/genptr.c | 155 ++++++++
target/hexagon/hex_interrupts.c | 371 ++++++++++++++++++
target/hexagon/hex_mmu.c | 268 +++++++++++++
target/hexagon/machine.c | 32 ++
target/hexagon/op_helper.c | 146 ++++++-
target/hexagon/translate.c | 56 ++-
target/hexagon/gen_analyze_funcs.py | 14 +-
target/hexagon/gen_helper_funcs.py | 26 +-
target/hexagon/gen_helper_protos.py | 23 +-
target/hexagon/gen_idef_parser_funcs.py | 2 +
target/hexagon/gen_op_attribs.py | 2 +-
target/hexagon/gen_opcodes_def.py | 5 +-
target/hexagon/gen_tcg_funcs.py | 35 +-
target/hexagon/hex_common.py | 181 ++++++++-
target/hexagon/imported/encode_pp.def | 128 ++++++-
target/hexagon/imported/macros.def | 482 +++++++++++++++++++++++-
target/hexagon/imported/system.idef | 244 +++++++++++-
target/hexagon/meson.build | 13 +-
46 files changed, 3802 insertions(+), 110 deletions(-)
create mode 100644 docs/devel/hexagon-sys.rst
create mode 100644 docs/system/hexagon/cdsp.rst
create mode 100644 docs/system/hexagon/emulation.rst
create mode 100644 docs/system/target-hexagon.rst
create mode 100644 include/hw/hexagon/hexagon_tlb.h
create mode 100644 target/hexagon/cpu_helper.h
create mode 100644 target/hexagon/gen_tcg_sys.h
create mode 100644 target/hexagon/hex_interrupts.h
create mode 100644 target/hexagon/hex_mmu.h
create mode 100644 target/hexagon/sys_macros.h
create mode 100644 target/hexagon/cpu_helper.c
create mode 100644 target/hexagon/hex_interrupts.c
create mode 100644 target/hexagon/hex_mmu.c
create mode 100644 target/hexagon/machine.c
mode change 100755 => 100644 target/hexagon/imported/macros.def
--
2.34.1