target/riscv/tcg/tcg-cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
We did a recent change to disable svpbmt if satp_mode < sv39 that was
discovered via a gitlab report.
This time we don't have an opened bug but the problem is similar: RISC-V
privileged ISA, chapter '"Svnapot" Extension for NAPOT Translation
Contiguity, Version 1.0' states:
"The Svnapot extension depends on the Sv39 extension."
Do the same thing with svnapot, including the user warning in case we
try to enable it without the required satp_mode:
$ ./build/qemu-system-riscv64 -M virt,dumpdtb=fdt.dtb \
-cpu max,sv39=off,sv48=off,sv57=off,sv64=off,svnapot=on
qemu-system-riscv64: warning: svnapot requires at least satp sv39, current satp mode: none
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/tcg/tcg-cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f8b2f04a94..c3006bccb7 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -847,6 +847,16 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
riscv_cpu_is_32bit(cpu)));
}
}
+
+ if (cpu->cfg.ext_svnapot && cpu->cfg.max_satp_mode < VM_1_10_SV39) {
+ cpu->cfg.ext_svnapot = false;
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_svnapot))) {
+ warn_report("svnapot requires at least satp sv39, "
+ "current satp mode: %s",
+ satp_mode_str(cpu->cfg.max_satp_mode,
+ riscv_cpu_is_32bit(cpu)));
+ }
+ }
#endif
/*
* Disable isa extensions based on priv spec after we
--
2.43.0
On Thu, 28 May 2026, at 7:30 AM, Daniel Henrique Barboza wrote:
> We did a recent change to disable svpbmt if satp_mode < sv39 that was
> discovered via a gitlab report.
>
> This time we don't have an opened bug but the problem is similar: RISC-V
> privileged ISA, chapter '"Svnapot" Extension for NAPOT Translation
> Contiguity, Version 1.0' states:
>
> "The Svnapot extension depends on the Sv39 extension."
>
> Do the same thing with svnapot, including the user warning in case we
> try to enable it without the required satp_mode:
>
> $ ./build/qemu-system-riscv64 -M virt,dumpdtb=fdt.dtb \
> -cpu max,sv39=off,sv48=off,sv57=off,sv64=off,svnapot=on
> qemu-system-riscv64: warning: svnapot requires at least satp sv39, current satp mode: none
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index f8b2f04a94..c3006bccb7 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -847,6 +847,16 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> riscv_cpu_is_32bit(cpu)));
> }
> }
> +
> + if (cpu->cfg.ext_svnapot && cpu->cfg.max_satp_mode < VM_1_10_SV39) {
> + cpu->cfg.ext_svnapot = false;
> + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_svnapot))) {
> + warn_report("svnapot requires at least satp sv39, "
> + "current satp mode: %s",
> + satp_mode_str(cpu->cfg.max_satp_mode,
> + riscv_cpu_is_32bit(cpu)));
> + }
> + }
> #endif
> /*
> * Disable isa extensions based on priv spec after we
> --
> 2.43.0
>
>
>
On Thu, 28 May 2026, at 7:30 AM, Daniel Henrique Barboza wrote:
> We did a recent change to disable svpbmt if satp_mode < sv39 that was
> discovered via a gitlab report.
>
> This time we don't have an opened bug but the problem is similar: RISC-V
> privileged ISA, chapter '"Svnapot" Extension for NAPOT Translation
> Contiguity, Version 1.0' states:
>
> "The Svnapot extension depends on the Sv39 extension."
>
> Do the same thing with svnapot, including the user warning in case we
> try to enable it without the required satp_mode:
>
> $ ./build/qemu-system-riscv64 -M virt,dumpdtb=fdt.dtb \
> -cpu max,sv39=off,sv48=off,sv57=off,sv64=off,svnapot=on
> qemu-system-riscv64: warning: svnapot requires at least satp sv39, current satp mode: none
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index f8b2f04a94..c3006bccb7 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -847,6 +847,16 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> riscv_cpu_is_32bit(cpu)));
> }
> }
> +
> + if (cpu->cfg.ext_svnapot && cpu->cfg.max_satp_mode < VM_1_10_SV39) {
> + cpu->cfg.ext_svnapot = false;
> + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_svnapot))) {
> + warn_report("svnapot requires at least satp sv39, "
> + "current satp mode: %s",
> + satp_mode_str(cpu->cfg.max_satp_mode,
> + riscv_cpu_is_32bit(cpu)));
> + }
> + }
> #endif
> /*
> * Disable isa extensions based on priv spec after we
> --
> 2.43.0
>
>
>
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