The following changes since commit 3f89b5de5b1ff16873bcda7d5f3ff5b9164f691e:

  Merge tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu into staging (2026-05-26 13:20:15 -0400)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/single-binary-20260527

for you to fetch changes up to 5505e1cd0248fd87cbdbb16bb322a34db16d3e98:

  MAINTAINERS: Update PhilMD's email address (2026-05-27 12:27:22 +0200)

All following checkpatch.pl warnings ignored since files are covered:

  WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

----------------------------------------------------------------
Various patches related to single binary effort:

- Preparatory patches to build RISCV machines once
- Build ARM machines once
- Build ARM 'max' CPU once
- Few MAINTAINERS updates
----------------------------------------------------------------

Anton Blanchard (1):
  target/riscv: Use float_raise

Anton Johansson (6):
  hw/riscv: Register generic riscv[32|64] QOM interfaces
  hw/riscv: Add macros and globals for simplifying machine definitions
  hw/core: Add riscv[32|64] to "none" machine
  hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries
  configs/target: Implement per-binary TargetInfo structure for riscv
  target-info: Add target_riscv64()

Brian Cain (1):
  MAINTAINERS: update qualcomm git tree URL

Djordje Todorovic (1):
  target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks

Philippe Mathieu-Daudé (23):
  hw/riscv/spike: Use 'max' CPU type by default
  target/hppa: Use DisasContext::mo_align in system emulation
  target/hppa: Inline UNALIGN() macro
  hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()
  hw/arm/raspi: Build objects once
  hw/arm/aspeed: Do not realize 64-bit CPU types under QTest
  hw/arm/aspeed: Build objects once
  hw/arm/meson: Remove now unused arm_ss[] source set
  target/arm: Introduce common system/user meson source set
  target/arm: Build gdbstub64.o as common object
  target/arm: Build cpu64.o as common object
  target/arm: Extract common code related to 'max' CPU
  target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type
  target/arm: Implement DBGDEVID* registers in max AArch32 CPU
  target/arm: Only set %kvm_target when KVM is enabled
  target/arm: Factor aarch64_aa32_a57_init() out
  target/arm: Re-use common aarch64_aa32_a57_init() helper
  target/arm: Define 'max' CPU type in cpu-max.c
  target/arm: Build cpu32-system.o as common object
  target/arm: Build cpu-max.c once
  tests/tcg: Explicitly check for 64-bit z/Architecture
  MAINTAINERS: Remove PhilMD from firmware sections
  MAINTAINERS: Update PhilMD's email address

 MAINTAINERS                                |  67 +++---
 include/hw/riscv/machines-qom.h            |  46 ++++
 include/qemu/target-info.h                 |   7 +
 target/arm/internals.h                     |   2 +
 target/riscv/cpu_bits.h                    |   2 +
 tests/tcg/multiarch/nop_func.h             |   2 +-
 configs/targets/riscv32-softmmu.c          |  26 +++
 configs/targets/riscv64-softmmu.c          |  26 +++
 hw/arm/aspeed_ast27x0.c                    |  14 ++
 hw/arm/bcm2836.c                           |  14 +-
 hw/arm/raspi.c                             |   4 -
 hw/core/null-machine.c                     |   3 +
 hw/riscv/boston-aia.c                      |   3 +-
 hw/riscv/microblaze-v-generic.c            |   3 +-
 hw/riscv/microchip_pfsoc.c                 |   2 +
 hw/riscv/opentitan.c                       |   2 +
 hw/riscv/shakti_c.c                        |   2 +
 hw/riscv/sifive_e.c                        |   2 +
 hw/riscv/sifive_u.c                        |   2 +
 hw/riscv/spike.c                           |   4 +-
 hw/riscv/virt.c                            |   3 +
 hw/riscv/xiangshan_kmh.c                   |   2 +
 target-info-qom.c                          |   9 +
 target-info.c                              |   5 +
 target/arm/cpu-max.c                       | 241 +++++++++++++++++++++
 target/arm/cpu64.c                         |  80 +------
 target/arm/tcg/{cpu32.c => cpu32-system.c} | 174 +--------------
 target/arm/tcg/stubs32.c                   |  10 +
 target/hppa/translate.c                    |  23 +-
 target/riscv/machine.c                     |  19 +-
 target/riscv/vector_helper.c               |  35 ++-
 .mailmap                                   |   7 +-
 configs/targets/meson.build                |   1 +
 contrib/gitdm/group-map-individuals        |   1 +
 hw/arm/meson.build                         |  15 +-
 target/arm/meson.build                     |  26 ++-
 target/arm/tcg/meson.build                 |  57 ++---
 37 files changed, 550 insertions(+), 391 deletions(-)
 create mode 100644 include/hw/riscv/machines-qom.h
 create mode 100644 configs/targets/riscv32-softmmu.c
 create mode 100644 configs/targets/riscv64-softmmu.c
 create mode 100644 target/arm/cpu-max.c
 rename target/arm/tcg/{cpu32.c => cpu32-system.c} (81%)

-- 
2.53.0

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.