hw/riscv: Inline TYPE_RISCV_CPU_BASE definition

[PATCH 0/4] hw/riscv: Inline TYPE_RISCV_CPU_BASE definition

Philippe Mathieu-Daudé posted 4 patches 4 days, 6 hours ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260526095731.63525-1-philmd@linaro.org

Maintainers: Sai Pavan Boddu <sai.pavan.boddu@amd.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>

include/qemu/target-info.h      | 7 +++++++
target/riscv/cpu.h              | 6 ------
hw/riscv/microblaze-v-generic.c | 4 +++-
hw/riscv/spike.c                | 2 +-
hw/riscv/virt.c                 | 4 +++-
target-info.c                   | 5 +++++
6 files changed, 19 insertions(+), 9 deletions(-)

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[PATCH 0/4] hw/riscv: Inline TYPE_RISCV_CPU_BASE definition

Posted by Philippe Mathieu-Daudé 4 days, 6 hours ago

Inline TYPE_RISCV_CPU_BASE in preparation of "single-binary:
Compile hw/riscv once":
https://lore.kernel.org/qemu-devel/20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng/

Anton Johansson (1):
  target-info: Add target_riscv64()

Philippe Mathieu-Daudé (3):
  hw/riscv/spike: Use 'max' CPU type by default
  hw/riscv/microblaze-v: Use RV32I / RV64I CPU type by default
  hw/riscv/virt: Inline TYPE_RISCV_CPU_BASE definition

 include/qemu/target-info.h      | 7 +++++++
 target/riscv/cpu.h              | 6 ------
 hw/riscv/microblaze-v-generic.c | 4 +++-
 hw/riscv/spike.c                | 2 +-
 hw/riscv/virt.c                 | 4 +++-
 target-info.c                   | 5 +++++
 6 files changed, 19 insertions(+), 9 deletions(-)

-- 
2.53.0

Re: [PATCH 0/4] hw/riscv: Inline TYPE_RISCV_CPU_BASE definition

Posted by Anton Johansson via qemu development 4 days ago

On 26/05/26, Philippe Mathieu-Daudé wrote:
> Inline TYPE_RISCV_CPU_BASE in preparation of "single-binary:
> Compile hw/riscv once":
> https://lore.kernel.org/qemu-devel/20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng/
> 
> Anton Johansson (1):
>   target-info: Add target_riscv64()
> 
> Philippe Mathieu-Daudé (3):
>   hw/riscv/spike: Use 'max' CPU type by default
>   hw/riscv/microblaze-v: Use RV32I / RV64I CPU type by default
>   hw/riscv/virt: Inline TYPE_RISCV_CPU_BASE definition
> 
>  include/qemu/target-info.h      | 7 +++++++
>  target/riscv/cpu.h              | 6 ------
>  hw/riscv/microblaze-v-generic.c | 4 +++-
>  hw/riscv/spike.c                | 2 +-
>  hw/riscv/virt.c                 | 4 +++-
>  target-info.c                   | 5 +++++
>  6 files changed, 19 insertions(+), 9 deletions(-)
> 
> -- 
> 2.53.0
> 

Series:

  Reviewed-by: Anton Johansson <anjo@rev.ng>