target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault

[PATCH] target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault

Posted by Daniel Henrique Barboza 1 week ago

promote_load_fault() is missing the promotion of misaligned AMO load
addresses, i.e. RISCV_EXCP_LOAD_ADDR_MIS should be promoted to
RISCV_EXCP_STORE_AMO_ADDR_MIS when RISCV_UW2_ALWAYS_STORE_AMO (i.e.
always_storeamo is true).

All other load AMO faults are already being covered.

Cc: qemu-stable@nongnu.org
Fixes: 98f21c30f5 ("target/riscv: AMO operations always raise store/AMO fault")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3503
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 target/riscv/cpu_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 17305e1bb7..aa4cbfcf40 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -2174,6 +2174,9 @@ static target_ulong promote_load_fault(target_ulong orig_cause)
 
     case RISCV_EXCP_LOAD_PAGE_FAULT:
         return RISCV_EXCP_STORE_PAGE_FAULT;
+
+    case RISCV_EXCP_LOAD_ADDR_MIS:
+        return RISCV_EXCP_STORE_AMO_ADDR_MIS;
     }
 
     /* if no promotion, return original cause */
-- 
2.43.0

Re: [PATCH] target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault

Posted by Alistair Francis 3 days, 15 hours ago

On Fri, 2026-05-22 at 15:13 -0300, Daniel Henrique Barboza wrote:
> promote_load_fault() is missing the promotion of misaligned AMO load
> addresses, i.e. RISCV_EXCP_LOAD_ADDR_MIS should be promoted to
> RISCV_EXCP_STORE_AMO_ADDR_MIS when RISCV_UW2_ALWAYS_STORE_AMO (i.e.
> always_storeamo is true).
> 
> All other load AMO faults are already being covered.
> 
> Cc: qemu-stable@nongnu.org
> Fixes: 98f21c30f5 ("target/riscv: AMO operations always raise
> store/AMO fault")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3503
> Signed-off-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu_helper.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 17305e1bb7..aa4cbfcf40 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -2174,6 +2174,9 @@ static target_ulong
> promote_load_fault(target_ulong orig_cause)
>  
>      case RISCV_EXCP_LOAD_PAGE_FAULT:
>          return RISCV_EXCP_STORE_PAGE_FAULT;
> +
> +    case RISCV_EXCP_LOAD_ADDR_MIS:
> +        return RISCV_EXCP_STORE_AMO_ADDR_MIS;
>      }
>  
>      /* if no promotion, return original cause */

Re: [PATCH] target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault

Posted by Alistair Francis 3 days, 16 hours ago

On Fri, 2026-05-22 at 15:13 -0300, Daniel Henrique Barboza wrote:
> promote_load_fault() is missing the promotion of misaligned AMO load
> addresses, i.e. RISCV_EXCP_LOAD_ADDR_MIS should be promoted to
> RISCV_EXCP_STORE_AMO_ADDR_MIS when RISCV_UW2_ALWAYS_STORE_AMO (i.e.
> always_storeamo is true).
> 
> All other load AMO faults are already being covered.
> 
> Cc: qemu-stable@nongnu.org
> Fixes: 98f21c30f5 ("target/riscv: AMO operations always raise
> store/AMO fault")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3503
> Signed-off-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 17305e1bb7..aa4cbfcf40 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -2174,6 +2174,9 @@ static target_ulong
> promote_load_fault(target_ulong orig_cause)
>  
>      case RISCV_EXCP_LOAD_PAGE_FAULT:
>          return RISCV_EXCP_STORE_PAGE_FAULT;
> +
> +    case RISCV_EXCP_LOAD_ADDR_MIS:
> +        return RISCV_EXCP_STORE_AMO_ADDR_MIS;
>      }
>  
>      /* if no promotion, return original cause */

Re: [PATCH] target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault

Posted by Chao Liu 5 days, 12 hours ago

On Fri, May 22, 2026 at 03:13:53PM +0800, Daniel Henrique Barboza wrote:
> promote_load_fault() is missing the promotion of misaligned AMO load
> addresses, i.e. RISCV_EXCP_LOAD_ADDR_MIS should be promoted to
> RISCV_EXCP_STORE_AMO_ADDR_MIS when RISCV_UW2_ALWAYS_STORE_AMO (i.e.
> always_storeamo is true).
> 
> All other load AMO faults are already being covered.
> 
> Cc: qemu-stable@nongnu.org
> Fixes: 98f21c30f5 ("target/riscv: AMO operations always raise store/AMO fault")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3503
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>


> ---
>  target/riscv/cpu_helper.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 17305e1bb7..aa4cbfcf40 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -2174,6 +2174,9 @@ static target_ulong promote_load_fault(target_ulong orig_cause)
>  
>      case RISCV_EXCP_LOAD_PAGE_FAULT:
>          return RISCV_EXCP_STORE_PAGE_FAULT;
> +
> +    case RISCV_EXCP_LOAD_ADDR_MIS:
> +        return RISCV_EXCP_STORE_AMO_ADDR_MIS;
>      }
>  
>      /* if no promotion, return original cause */
> -- 
> 2.43.0
>