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[PATCH v2] target/riscv: Use float_raise

Anton Blanchard posted 1 patch 1 week, 2 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260521110824.1091323-1-antonb@tenstorrent.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>
target/riscv/vector_helper.c | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
[PATCH v2] target/riscv: Use float_raise
Posted by Anton Blanchard 1 week, 2 days ago 
---
 target/riscv/vector_helper.c | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c4e150635e..d1be0682fe 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4084,7 +4084,7 @@ static bfloat16 frsqrt7_h_bf16(bfloat16 f, float_status *s)
         (bfloat16_is_infinity(f) && sign) ||
         (bfloat16_is_normal(f) && sign) ||
         (bfloat16_is_zero_or_denormal(f) && !bfloat16_is_zero(f) && sign)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return bfloat16_default_nan(s);
     }
 
@@ -4095,7 +4095,7 @@ static bfloat16 frsqrt7_h_bf16(bfloat16 f, float_status *s)
 
     /* frsqrt7(+-0) = +-inf */
     if (bfloat16_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return bfloat16_set_sign(bfloat16_infinity, sign);
     }
 
@@ -4124,7 +4124,7 @@ static float16 frsqrt7_h(float16 f, float_status *s)
         (float16_is_infinity(f) && sign) ||
         (float16_is_normal(f) && sign) ||
         (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return float16_default_nan(s);
     }
 
@@ -4135,7 +4135,7 @@ static float16 frsqrt7_h(float16 f, float_status *s)
 
     /* frsqrt7(+-0) = +-inf */
     if (float16_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return float16_set_sign(float16_infinity, sign);
     }
 
@@ -4164,7 +4164,7 @@ static float32 frsqrt7_s(float32 f, float_status *s)
         (float32_is_infinity(f) && sign) ||
         (float32_is_normal(f) && sign) ||
         (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return float32_default_nan(s);
     }
 
@@ -4175,7 +4175,7 @@ static float32 frsqrt7_s(float32 f, float_status *s)
 
     /* frsqrt7(+-0) = +-inf */
     if (float32_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return float32_set_sign(float32_infinity, sign);
     }
 
@@ -4204,7 +4204,7 @@ static float64 frsqrt7_d(float64 f, float_status *s)
         (float64_is_infinity(f) && sign) ||
         (float64_is_normal(f) && sign) ||
         (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return float64_default_nan(s);
     }
 
@@ -4215,7 +4215,7 @@ static float64 frsqrt7_d(float64 f, float_status *s)
 
     /* frsqrt7(+-0) = +-inf */
     if (float64_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return float64_set_sign(float64_infinity, sign);
     }
 
@@ -4285,8 +4285,7 @@ static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
              * Overflow to inf or max value of same sign,
              * depending on sign and rounding mode.
              */
-            s->float_exception_flags |= (float_flag_inexact |
-                                         float_flag_overflow);
+            float_raise(float_flag_inexact | float_flag_overflow, s);
 
             if ((s->float_rounding_mode == float_round_to_zero) ||
                 ((s->float_rounding_mode == float_round_down) && !sign) ||
@@ -4338,13 +4337,13 @@ static bfloat16 frec7_h_bf16(bfloat16 f, float_status *s)
 
     /* frec7(+-0) = +-inf */
     if (bfloat16_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return bfloat16_set_sign(bfloat16_infinity, sign);
     }
 
     /* frec7(sNaN) = canonical NaN */
     if (bfloat16_is_signaling_nan(f, s)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return bfloat16_default_nan(s);
     }
 
@@ -4370,13 +4369,13 @@ static float16 frec7_h(float16 f, float_status *s)
 
     /* frec7(+-0) = +-inf */
     if (float16_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return float16_set_sign(float16_infinity, sign);
     }
 
     /* frec7(sNaN) = canonical NaN */
     if (float16_is_signaling_nan(f, s)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return float16_default_nan(s);
     }
 
@@ -4402,13 +4401,13 @@ static float32 frec7_s(float32 f, float_status *s)
 
     /* frec7(+-0) = +-inf */
     if (float32_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return float32_set_sign(float32_infinity, sign);
     }
 
     /* frec7(sNaN) = canonical NaN */
     if (float32_is_signaling_nan(f, s)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return float32_default_nan(s);
     }
 
@@ -4434,13 +4433,13 @@ static float64 frec7_d(float64 f, float_status *s)
 
     /* frec7(+-0) = +-inf */
     if (float64_is_zero(f)) {
-        s->float_exception_flags |= float_flag_divbyzero;
+        float_raise(float_flag_divbyzero, s);
         return float64_set_sign(float64_infinity, sign);
     }
 
     /* frec7(sNaN) = canonical NaN */
     if (float64_is_signaling_nan(f, s)) {
-        s->float_exception_flags |= float_flag_invalid;
+        float_raise(float_flag_invalid, s);
         return float64_default_nan(s);
     }
 
-- 
2.34.1
Re: [PATCH v2] target/riscv: Use float_raise
Posted by Max Chou 3 days, 15 hours ago 
Reviewed-by: Max Chou <max.chou@sifive.com>

On 2026-05-21 11:08, Anton Blanchard wrote:
> 
> 
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/riscv/vector_helper.c | 35 +++++++++++++++++------------------
>  1 file changed, 17 insertions(+), 18 deletions(-)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index c4e150635e..d1be0682fe 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4084,7 +4084,7 @@ static bfloat16 frsqrt7_h_bf16(bfloat16 f, float_status *s)
>          (bfloat16_is_infinity(f) && sign) ||
>          (bfloat16_is_normal(f) && sign) ||
>          (bfloat16_is_zero_or_denormal(f) && !bfloat16_is_zero(f) && sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return bfloat16_default_nan(s);
>      }
>  
> @@ -4095,7 +4095,7 @@ static bfloat16 frsqrt7_h_bf16(bfloat16 f, float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (bfloat16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return bfloat16_set_sign(bfloat16_infinity, sign);
>      }
>  
> @@ -4124,7 +4124,7 @@ static float16 frsqrt7_h(float16 f, float_status *s)
>          (float16_is_infinity(f) && sign) ||
>          (float16_is_normal(f) && sign) ||
>          (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float16_default_nan(s);
>      }
>  
> @@ -4135,7 +4135,7 @@ static float16 frsqrt7_h(float16 f, float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (float16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float16_set_sign(float16_infinity, sign);
>      }
>  
> @@ -4164,7 +4164,7 @@ static float32 frsqrt7_s(float32 f, float_status *s)
>          (float32_is_infinity(f) && sign) ||
>          (float32_is_normal(f) && sign) ||
>          (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float32_default_nan(s);
>      }
>  
> @@ -4175,7 +4175,7 @@ static float32 frsqrt7_s(float32 f, float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (float32_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float32_set_sign(float32_infinity, sign);
>      }
>  
> @@ -4204,7 +4204,7 @@ static float64 frsqrt7_d(float64 f, float_status *s)
>          (float64_is_infinity(f) && sign) ||
>          (float64_is_normal(f) && sign) ||
>          (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float64_default_nan(s);
>      }
>  
> @@ -4215,7 +4215,7 @@ static float64 frsqrt7_d(float64 f, float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (float64_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float64_set_sign(float64_infinity, sign);
>      }
>  
> @@ -4285,8 +4285,7 @@ static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
>               * Overflow to inf or max value of same sign,
>               * depending on sign and rounding mode.
>               */
> -            s->float_exception_flags |= (float_flag_inexact |
> -                                         float_flag_overflow);
> +            float_raise(float_flag_inexact | float_flag_overflow, s);
>  
>              if ((s->float_rounding_mode == float_round_to_zero) ||
>                  ((s->float_rounding_mode == float_round_down) && !sign) ||
> @@ -4338,13 +4337,13 @@ static bfloat16 frec7_h_bf16(bfloat16 f, float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (bfloat16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return bfloat16_set_sign(bfloat16_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (bfloat16_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return bfloat16_default_nan(s);
>      }
>  
> @@ -4370,13 +4369,13 @@ static float16 frec7_h(float16 f, float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (float16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float16_set_sign(float16_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (float16_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float16_default_nan(s);
>      }
>  
> @@ -4402,13 +4401,13 @@ static float32 frec7_s(float32 f, float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (float32_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float32_set_sign(float32_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (float32_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float32_default_nan(s);
>      }
>  
> @@ -4434,13 +4433,13 @@ static float64 frec7_d(float64 f, float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (float64_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float64_set_sign(float64_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (float64_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float64_default_nan(s);
>      }
>  
> -- 
> 2.34.1
Re: [PATCH v2] target/riscv: Use float_raise
Posted by Alistair Francis 3 days, 16 hours ago 
You are missing a Signed-off-by line

Alistair

On Thu, 2026-05-21 at 11:08 +0000, Anton Blanchard wrote:
> ---
>  target/riscv/vector_helper.c | 35 +++++++++++++++++-----------------
> -
>  1 file changed, 17 insertions(+), 18 deletions(-)
> 
> diff --git a/target/riscv/vector_helper.c
> b/target/riscv/vector_helper.c
> index c4e150635e..d1be0682fe 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4084,7 +4084,7 @@ static bfloat16 frsqrt7_h_bf16(bfloat16 f,
> float_status *s)
>          (bfloat16_is_infinity(f) && sign) ||
>          (bfloat16_is_normal(f) && sign) ||
>          (bfloat16_is_zero_or_denormal(f) && !bfloat16_is_zero(f) &&
> sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return bfloat16_default_nan(s);
>      }
>  
> @@ -4095,7 +4095,7 @@ static bfloat16 frsqrt7_h_bf16(bfloat16 f,
> float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (bfloat16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return bfloat16_set_sign(bfloat16_infinity, sign);
>      }
>  
> @@ -4124,7 +4124,7 @@ static float16 frsqrt7_h(float16 f,
> float_status *s)
>          (float16_is_infinity(f) && sign) ||
>          (float16_is_normal(f) && sign) ||
>          (float16_is_zero_or_denormal(f) && !float16_is_zero(f) &&
> sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float16_default_nan(s);
>      }
>  
> @@ -4135,7 +4135,7 @@ static float16 frsqrt7_h(float16 f,
> float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (float16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float16_set_sign(float16_infinity, sign);
>      }
>  
> @@ -4164,7 +4164,7 @@ static float32 frsqrt7_s(float32 f,
> float_status *s)
>          (float32_is_infinity(f) && sign) ||
>          (float32_is_normal(f) && sign) ||
>          (float32_is_zero_or_denormal(f) && !float32_is_zero(f) &&
> sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float32_default_nan(s);
>      }
>  
> @@ -4175,7 +4175,7 @@ static float32 frsqrt7_s(float32 f,
> float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (float32_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float32_set_sign(float32_infinity, sign);
>      }
>  
> @@ -4204,7 +4204,7 @@ static float64 frsqrt7_d(float64 f,
> float_status *s)
>          (float64_is_infinity(f) && sign) ||
>          (float64_is_normal(f) && sign) ||
>          (float64_is_zero_or_denormal(f) && !float64_is_zero(f) &&
> sign)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float64_default_nan(s);
>      }
>  
> @@ -4215,7 +4215,7 @@ static float64 frsqrt7_d(float64 f,
> float_status *s)
>  
>      /* frsqrt7(+-0) = +-inf */
>      if (float64_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float64_set_sign(float64_infinity, sign);
>      }
>  
> @@ -4285,8 +4285,7 @@ static uint64_t frec7(uint64_t f, int exp_size,
> int frac_size,
>               * Overflow to inf or max value of same sign,
>               * depending on sign and rounding mode.
>               */
> -            s->float_exception_flags |= (float_flag_inexact |
> -                                         float_flag_overflow);
> +            float_raise(float_flag_inexact | float_flag_overflow,
> s);
>  
>              if ((s->float_rounding_mode == float_round_to_zero) ||
>                  ((s->float_rounding_mode == float_round_down) &&
> !sign) ||
> @@ -4338,13 +4337,13 @@ static bfloat16 frec7_h_bf16(bfloat16 f,
> float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (bfloat16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return bfloat16_set_sign(bfloat16_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (bfloat16_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return bfloat16_default_nan(s);
>      }
>  
> @@ -4370,13 +4369,13 @@ static float16 frec7_h(float16 f,
> float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (float16_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float16_set_sign(float16_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (float16_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float16_default_nan(s);
>      }
>  
> @@ -4402,13 +4401,13 @@ static float32 frec7_s(float32 f,
> float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (float32_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float32_set_sign(float32_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (float32_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float32_default_nan(s);
>      }
>  
> @@ -4434,13 +4433,13 @@ static float64 frec7_d(float64 f,
> float_status *s)
>  
>      /* frec7(+-0) = +-inf */
>      if (float64_is_zero(f)) {
> -        s->float_exception_flags |= float_flag_divbyzero;
> +        float_raise(float_flag_divbyzero, s);
>          return float64_set_sign(float64_infinity, sign);
>      }
>  
>      /* frec7(sNaN) = canonical NaN */
>      if (float64_is_signaling_nan(f, s)) {
> -        s->float_exception_flags |= float_flag_invalid;
> +        float_raise(float_flag_invalid, s);
>          return float64_default_nan(s);
>      }
>  
Re: [PATCH v2] target/riscv: Use float_raise
Posted by Philippe Mathieu-Daudé 3 days, 11 hours ago 
On 27/5/26 02:46, Alistair Francis wrote:
> 
> You are missing a Signed-off-by line

v1 had it, I suppose v2 simply had a workflow issue:
https://lore.kernel.org/qemu-devel/20260521074016.1065645-1-antonb@tenstorrent.com/

I'll queue this single patch to save all of us time ;)

Thanks,

Phil.

> 
> Alistair
> 
> On Thu, 2026-05-21 at 11:08 +0000, Anton Blanchard wrote:
>> ---
>>   target/riscv/vector_helper.c | 35 +++++++++++++++++-----------------
>> -
>>   1 file changed, 17 insertions(+), 18 deletions(-)
Re: [PATCH v2] target/riscv: Use float_raise
Posted by Philippe Mathieu-Daudé 1 week, 2 days ago 
On 21/5/26 13:08, Anton Blanchard wrote:

Use float_raise instead of open coding it.

Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> ---
>   target/riscv/vector_helper.c | 35 +++++++++++++++++------------------
>   1 file changed, 17 insertions(+), 18 deletions(-)

Patchew 2.1-devel-ea86937

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