Since v10:
- addressed rth review comments (rewording comment)
- pass gen_atomic_*() in do_atomic_ld()
- use tcg_zero_i128() in ZCB*
- re-order TRANS(trans_lx) lines

Respinning first half of James v10, adding tests with each
patch modifying an instruction instead of all at the end.
Split SEQNE/SEQNEI patch to ease review.

Based-on: rth/tcg-next

James Hilliard (23):
  linux-user/mips: implement sysmips(MIPS_FLUSH_CACHE)
  linux-user/mips: implement sysmips(MIPS_ATOMIC_SET)
  linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses
  target/mips: expose Octeon68XX floating-point support
  tests/tcg/mips: add Octeon instruction smoke test
  target/mips: fix Octeon arithmetic destination handling
  target/mips: drop Octeon zero-register fast paths
  target/mips: split Octeon SEQ/SNE decode
  target/mips: split Octeon SEQI/SNEI decode
  target/mips: add Octeon LBX instruction
  target/mips: add Octeon LHUX instruction
  target/mips: add Octeon LWUX instruction
  target/mips: add Octeon SAA instruction
  target/mips: add Octeon SAAD instruction
  target/mips: add Octeon ZCB and ZCBT instructions
  target/mips: add Octeon multiplier state
  target/mips: add Octeon MTM instructions
  target/mips: add Octeon MTP instructions
  target/mips: add Octeon VMULU instruction
  target/mips: add Octeon VMM0 instruction
  target/mips: add Octeon V3MULU instruction
  target/mips: add Octeon QMAC instructions
  target/mips: add Octeon LA* atomic instructions

Richard Henderson (1):
  tcg: Introduce tcg_gen_addN_i64

 MAINTAINERS                                   |   2 +-
 include/tcg/tcg-op-common.h                   |   1 +
 linux-user/mips/target_syscall.h              |   3 +
 linux-user/mips64/target_syscall.h            |   3 +
 target/mips/cpu.h                             |  16 +
 target/mips/tcg/translate.h                   |   2 +
 target/mips/tcg/octeon.decode                 |  54 ++-
 linux-user/mips/cpu_loop.c                    |   5 +
 linux-user/syscall.c                          |  56 +++
 target/mips/cpu.c                             |  10 +-
 target/mips/system/machine.c                  |  33 ++
 target/mips/tcg/octeon_translate.c            | 384 +++++++++++++++---
 target/mips/tcg/translate.c                   |  24 +-
 tcg/tcg-op.c                                  |  42 ++
 tests/tcg/mips/user/isa/octeon/octeon-insns.c | 204 ++++++++++
 target/mips/cpu-defs.c.inc                    |  10 +-
 tests/tcg/mips64/Makefile.target              |  20 +
 tests/tcg/mips64el/Makefile.target            |   8 +
 18 files changed, 817 insertions(+), 60 deletions(-)
 create mode 100644 tests/tcg/mips/user/isa/octeon/octeon-insns.c
 create mode 100644 tests/tcg/mips64/Makefile.target
 create mode 100644 tests/tcg/mips64el/Makefile.target

-- 
2.53.0

On 20/5/26 19:22, Philippe Mathieu-Daudé wrote:

> James Hilliard (23):
>    linux-user/mips: implement sysmips(MIPS_FLUSH_CACHE)
>    linux-user/mips: implement sysmips(MIPS_ATOMIC_SET)
>    linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses
>    target/mips: expose Octeon68XX floating-point support
>    tests/tcg/mips: add Octeon instruction smoke test
>    target/mips: fix Octeon arithmetic destination handling
>    target/mips: drop Octeon zero-register fast paths
>    target/mips: split Octeon SEQ/SNE decode
>    target/mips: split Octeon SEQI/SNEI decode
>    target/mips: add Octeon LBX instruction
>    target/mips: add Octeon LHUX instruction
>    target/mips: add Octeon LWUX instruction
>    target/mips: add Octeon SAA instruction
>    target/mips: add Octeon SAAD instruction
>    target/mips: add Octeon ZCB and ZCBT instructions
>    target/mips: add Octeon multiplier state
>    target/mips: add Octeon MTM instructions
>    target/mips: add Octeon MTP instructions
>    target/mips: add Octeon VMULU instruction
>    target/mips: add Octeon VMM0 instruction
>    target/mips: add Octeon V3MULU instruction
>    target/mips: add Octeon QMAC instructions
>    target/mips: add Octeon LA* atomic instructions
> 
> Richard Henderson (1):
>    tcg: Introduce tcg_gen_addN_i64

Series queued, thanks.