On Wed, 2026-05-20 at 14:53 +0200, Anton Johansson wrote:
> Hi,
>
> this is a first patchset moving towards single-binary support for
> riscv.
> Additional patchsets for hw/ and target/ are based on this one so
> it's
> best to make sure the approach taken is ok. Most patches in this set
> concern fields in CPUArchState which are either widened (usually to
> uint64_t) or fixed to a smaller size which handles all use cases.
>
> General purpose registers and fields mapped to TCG are dealt with by
> widening the type and applying an offset to tcg_global_mem_new() to
> correctly handle 32-bit targets on big endian hosts.
>
> Let me know what you think of the direction taken here and if you
> would
> prefer something else.
>
> Changes in v2:
> - Use BIT() to define misa extension bits in "Use 32 bits for misa
> extensions";
>
> - Squash "Fix size of mcause" into "Fix size of trivial
> CPUArchState
> fields";
>
> - Bump VMSTATE version_id and minimum_version_id for
> "cpu/pmp/entry",
> "cpu/pmp", "cpu/hyper", "cpu/vector", "cpu/rv128", "cpu/debug",
> "cpu/envcfg", "cpu/pmu", "cpu/jvt", "cpu/ssp", and "cpu".
> Migration
> from older versions is broken.
>
> Changes in v3:
> - Fix formatting issues during printing;
>
> - Move assert before extract64() in pmu_read_ctr();
>
> - Added patch 5/34 fixing a bug in rmw_cd_ctr_cfg() where bit 30 is
> zeroed instead of bit 62 (MHPMEVENTH_* vs MHPMEVENT_*);
>
> - Added privilege_mode_t typedef for storing PRV_* fields;
>
> - Added reviewed-bys.
>
> Changes in v4:
> - Used target-specific includes (target/riscv/*) for csr.h and
> debug.h (Philippe);
>
> - Migrated mcontext (Philippe), migration entry is added to
> existing
> patch modifiying mcontext (patch 29 "Fix size of trigger data");
>
> - Added reviewed-bys and acked-bys.
>
> Changes in v5:
> - Removed first 8 patches that were pulled out by Alistair;
>
> - Rebased on 20251103033713.904455-1-alistair.francis@wdc.com;
>
> - Added reviewed-bys and acked-bys.
>
> Changes in v6:
> - Rebased on master since previous base has since been merged.
>
> - Patch 2/27: `target/riscv: Fix size of vector CSRs`, changed
> arguments of functions in vector_helper.c to match new expected
> types.
>
> - Patch 4/27: `target/riscv: Fix size of frm and fflags`, update
> missed `rm` function arguments to match env type.
>
> - Patch 10/27: `target/riscv: Fix size of excp_uw2`, update
> missed `excp_uw2` function arguments to match env type.
>
> - Patch 12/27: `target/riscv: Fix size of priv`, update
> missed function arguments to use privilege_mode_t.
>
> - Patch 13/27: `target/riscv: Fix size of gei fields`, masking when
> assigning gei fields is widened to 64-bit as geilen is already
> verified to be smaller than the target long size, and an
> out-of-bounds shift would be UB anyway
>
> - Added patch 26/27 `target/riscv: Pass address as uint64_t in
> cpu_set_exception_base()` to handle a new exposed function in
> cpu.h
>
> - Added patch 27/27 `target/riscv: Fix pmp.h/cpu.h circular
> inclusion`
> to address a circular dependency between pmp.h and cpu.h.
>
> Changes in v7:
> - Change return type of riscv_cpu_xlen() from int to uint16_t
> (Philippe)
>
> - Update irq_overflow_left comment (Philippe)
>
> - Return RISCVException in externally facing CSR functions
> (Philippe).
>
> Anton Johansson (27):
> target/riscv: Fix size of gpr and gprh
> target/riscv: Fix size of vector CSRs
> target/riscv: Fix size of pc, load_[val|res]
> target/riscv: Fix size of frm and fflags
> target/riscv: Fix size of badaddr and bins
> target/riscv: Fix size of guest_phys_fault_addr
> target/riscv: Fix size of priv_ver and vext_ver
> target/riscv: Fix size of retxh
> target/riscv: Fix size of ssp
> target/riscv: Fix size of excp_uw2
> target/riscv: Fix size of sw_check_code
> target/riscv: Fix size of priv
> target/riscv: Fix size of gei fields
> target/riscv: Fix size of [m|s|vs]iselect fields
> target/riscv: Fix arguments to board IMSIC emulation callbacks
> target/riscv: Fix size of irq_overflow_left
> target/riscv: Indent PMUFixedCtrState correctly
> target/riscv: Replace target_ulong in riscv_cpu_get_trap_name()
> target/riscv: Replace target_ulong in riscv_ctr_add_entry()
> target/riscv: Fix size of trigger data
> target/riscv: Fix size of mseccfg
> target/riscv: Move debug.h include away from cpu.h
> target/riscv: Move CSR declarations to separate csr.h header
> target/riscv: Introduce externally facing CSR access functions
> target/riscv: Make pmp.h target_ulong agnostic
> target/riscv: Pass address as uint64_t in cpu_set_exception_base()
> target/riscv: Fix pmp.h/cpu.h circular inclusion
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 264 +++++++---------
> --
> target/riscv/csr.h | 102 +++++++
> target/riscv/debug.h | 2 -
> target/riscv/internals.h | 4 +-
> target/riscv/pmp.h | 23 +-
> target/riscv/pmu.h | 2 +-
> hw/intc/riscv_imsic.c | 34 +--
> hw/riscv/riscv_hart.c | 7 +-
> linux-user/riscv/signal.c | 5 +-
> target/riscv/cpu.c | 22 +-
> target/riscv/cpu_helper.c | 65 +++--
> target/riscv/csr.c | 93 +++---
> target/riscv/debug.c | 1 +
> target/riscv/fpu_helper.c | 10 +-
> target/riscv/gdbstub.c | 3 +-
> target/riscv/kvm/kvm-cpu.c | 1 +
> target/riscv/machine.c | 81 +++---
> target/riscv/mips_csr.c | 1 +
> target/riscv/monitor.c | 3 +-
> target/riscv/op_helper.c | 28 +-
> target/riscv/pmp.c | 14 +-
> target/riscv/pmu.c | 9 +-
> target/riscv/riscv-qmp-cmds.c | 1 +
> target/riscv/tcg/tcg-cpu.c | 1 +
> target/riscv/th_csr.c | 1 +
> target/riscv/translate.c | 60 ++--
> target/riscv/vector_helper.c | 125 +++++----
> .../riscv/insn_trans/trans_privileged.c.inc | 2 +-
> target/riscv/insn_trans/trans_rvi.c.inc | 16 +-
> target/riscv/insn_trans/trans_rvm.c.inc | 16 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 22 +-
> target/riscv/insn_trans/trans_rvzicfiss.c.inc | 22 +-
> 32 files changed, 585 insertions(+), 455 deletions(-)
> create mode 100644 target/riscv/csr.h