Series fully reviewed.

Since v7:
- Rebased on top of 8d3e31c0d57 (IDAU interface)

Since v6:
- Do not initialize Aspeed CPU in SoC realize (cdrx)

Since v5:
- Unify 'max' CPU type (rth, pm215)

Since v4:
- Add DEFINE_MACHINE_WITH_INTERFACES (Zoltan)
- Use GPtrArray for get_valid_cpu_type (Richard)
- Define InterfaceInfo[] arrays (Richard)
- Collect R-b tags

Since v3:
- QAPI structure renamed as QemuTargetInfo
- MachineClass::get_valid_cpu_types() runtime
- target_aarch64() checking SysEmuTarget value
- Remove CONFIG_TCG #ifdef'ry in hw/arm/

Since v2:
- More comments from Pierrick addressed
- Use GList to register valid CPUs list
- Remove all TARGET_AARCH64 uses in hw/arm/

Since v1:
- Dropped unrelated / irrelevant patches
- Addressed Pierrick comments
- Added R-b tag
- Only considering machines, not CPUs.

Available here, based on my pending patch queue:
https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v5

Matthew Penney (1):
  tests/qtest: fix discarded const qualifier warning

Philippe Mathieu-Daudé (17):
  hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()
  hw/arm/raspi: Build objects once
  hw/arm/aspeed: Do not realize 64-bit CPU types under QTest
  hw/arm/aspeed: Build objects once
  hw/arm/meson: Remove now unused arm_ss[] source set
  target/arm: Introduce common system/user meson source set
  target/arm: Build gdbstub64.o as common object
  target/arm: Build cpu64.o as common object
  target/arm: Extract common code related to 'max' CPU
  target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type
  target/arm: Implement DBGDEVID* registers in max AArch32 CPU
  target/arm: Only set %kvm_target when KVM is enabled
  target/arm: Factor aarch64_aa32_a57_init() out
  target/arm: Re-use common aarch64_aa32_a57_init() helper
  target/arm: Define 'max' CPU type in cpu-max.c
  target/arm: Build cpu32-system.o as common object
  target/arm: Build cpu-max.c once

 target/arm/internals.h                     |   2 +
 hw/arm/aspeed_ast27x0.c                    |  14 ++
 hw/arm/bcm2836.c                           |  14 +-
 hw/arm/raspi.c                             |   4 -
 target/arm/cpu-max.c                       | 241 +++++++++++++++++++++
 target/arm/cpu64.c                         |  80 +------
 target/arm/tcg/{cpu32.c => cpu32-system.c} | 174 +--------------
 target/arm/tcg/stubs32.c                   |  10 +
 tests/qtest/libqtest.c                     |   2 +-
 hw/arm/meson.build                         |  15 +-
 target/arm/meson.build                     |  26 ++-
 target/arm/tcg/meson.build                 |  57 ++---
 12 files changed, 319 insertions(+), 320 deletions(-)
 create mode 100644 target/arm/cpu-max.c
 rename target/arm/tcg/{cpu32.c => cpu32-system.c} (81%)

-- 
2.53.0

On Tue, 19 May 2026 at 15:46, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Series fully reviewed.

Since it's all reviewed, if you want to take it via
a single-binary pullreq you can have my
Acked-by: Peter Maydell <peter.maydell@linaro.org>

Otherwise I can take it in my next arm pullreq, but
that might be a while as I've just sent one.

-- PMM

On 26/5/26 17:55, Peter Maydell wrote:
> On Tue, 19 May 2026 at 15:46, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>>
>> Series fully reviewed.
> 
> Since it's all reviewed, if you want to take it via
> a single-binary pullreq you can have my
> Acked-by: Peter Maydell <peter.maydell@linaro.org>

Thanks!

> 
> Otherwise I can take it in my next arm pullreq, but
> that might be a while as I've just sent one.

Unfortunately an aspeed pull request got merged today which
also updates hw/arm/meson.build, so I need to respin another time.

On 19/5/26 16:45, Philippe Mathieu-Daudé wrote:
> Series fully reviewed.


> Matthew Penney (1):
>    tests/qtest: fix discarded const qualifier warning

The first patch is now committed as e68da5b7a2cd8f46; hopefully
this series still applies correctly, otherwise I can respin.

> Philippe Mathieu-Daudé (17):
>    hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()
>    hw/arm/raspi: Build objects once
>    hw/arm/aspeed: Do not realize 64-bit CPU types under QTest
>    hw/arm/aspeed: Build objects once
>    hw/arm/meson: Remove now unused arm_ss[] source set
>    target/arm: Introduce common system/user meson source set
>    target/arm: Build gdbstub64.o as common object
>    target/arm: Build cpu64.o as common object
>    target/arm: Extract common code related to 'max' CPU
>    target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type
>    target/arm: Implement DBGDEVID* registers in max AArch32 CPU
>    target/arm: Only set %kvm_target when KVM is enabled
>    target/arm: Factor aarch64_aa32_a57_init() out
>    target/arm: Re-use common aarch64_aa32_a57_init() helper
>    target/arm: Define 'max' CPU type in cpu-max.c
>    target/arm: Build cpu32-system.o as common object
>    target/arm: Build cpu-max.c once