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[PATCH] target/riscv: Update the local interrupt mask

alistair23@gmail.com posted 1 patch 2 weeks, 3 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260513051841.1671987-1-alistair.francis@wdc.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
[PATCH] target/riscv: Update the local interrupt mask
Posted by alistair23@gmail.com 2 weeks, 3 days ago 
From: Alistair Francis <alistair.francis@wdc.com>

The RISC-V spec describes bits 0-15 as standard fixed interrupts. The
AIA spec on the other hand describes bits 0-12 as standard fixed
interrupts. This conflict causes issues for us as we don't dynamically
determine if AIA is enabled when setting the *delegable_ints consts.

This means currently we incorrectly treat the LCOFIP bit as delegable,
even if AIA is disabled, which is incorrect (see the issues mentioned
below).

The AIA spec indicates that implementations can determine which bits of
13-63 in mvien are writable, so let's just make it bits 15-63 to match
the main spec.

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3133
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3134
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3135
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3138
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3140
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e1cd4a299c..db886aeed1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1777,13 +1777,13 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
 #define VSTOPI_NUM_SRCS 5
 
 /*
- * All core local interrupts except the fixed ones 0:12. This macro is for
+ * All core local interrupts except the fixed ones 0:15. This macro is for
  * virtual interrupts logic so please don't change this to avoid messing up
  * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and
  * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for
  * VS level`.
  */
-#define LOCAL_INTERRUPTS   (~0x1FFFULL)
+#define LOCAL_INTERRUPTS   (~0xFFFFULL)
 
 static const uint64_t delegable_ints =
     S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
-- 
2.53.0
Re: [PATCH] target/riscv: Update the local interrupt mask
Posted by Alistair Francis 1 week, 5 days ago 
On Wed, May 13, 2026 at 3:18 PM <alistair23@gmail.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The RISC-V spec describes bits 0-15 as standard fixed interrupts. The
> AIA spec on the other hand describes bits 0-12 as standard fixed
> interrupts. This conflict causes issues for us as we don't dynamically
> determine if AIA is enabled when setting the *delegable_ints consts.
>
> This means currently we incorrectly treat the LCOFIP bit as delegable,
> even if AIA is disabled, which is incorrect (see the issues mentioned
> below).
>
> The AIA spec indicates that implementations can determine which bits of
> 13-63 in mvien are writable, so let's just make it bits 15-63 to match
> the main spec.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3133
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3134
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3135
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3138
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3140
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e1cd4a299c..db886aeed1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1777,13 +1777,13 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
>  #define VSTOPI_NUM_SRCS 5
>
>  /*
> - * All core local interrupts except the fixed ones 0:12. This macro is for
> + * All core local interrupts except the fixed ones 0:15. This macro is for
>   * virtual interrupts logic so please don't change this to avoid messing up
>   * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and
>   * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for
>   * VS level`.
>   */
> -#define LOCAL_INTERRUPTS   (~0x1FFFULL)
> +#define LOCAL_INTERRUPTS   (~0xFFFFULL)
>
>  static const uint64_t delegable_ints =
>      S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
> --
> 2.53.0
>
Re: [PATCH] target/riscv: Update the local interrupt mask
Posted by Daniel Henrique Barboza 2 weeks, 2 days ago 

On 5/13/2026 2:18 AM, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The RISC-V spec describes bits 0-15 as standard fixed interrupts. The
> AIA spec on the other hand describes bits 0-12 as standard fixed
> interrupts. This conflict causes issues for us as we don't dynamically
> determine if AIA is enabled when setting the *delegable_ints consts.
> 
> This means currently we incorrectly treat the LCOFIP bit as delegable,
> even if AIA is disabled, which is incorrect (see the issues mentioned
> below).
> 
> The AIA spec indicates that implementations can determine which bits of
> 13-63 in mvien are writable, so let's just make it bits 15-63 to match
> the main spec.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3133
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3134
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3135
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3138
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3140
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/csr.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e1cd4a299c..db886aeed1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1777,13 +1777,13 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
>   #define VSTOPI_NUM_SRCS 5
>   
>   /*
> - * All core local interrupts except the fixed ones 0:12. This macro is for
> + * All core local interrupts except the fixed ones 0:15. This macro is for
>    * virtual interrupts logic so please don't change this to avoid messing up
>    * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and
>    * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for
>    * VS level`.
>    */
> -#define LOCAL_INTERRUPTS   (~0x1FFFULL)
> +#define LOCAL_INTERRUPTS   (~0xFFFFULL)
>   
>   static const uint64_t delegable_ints =
>       S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;

Patchew 2.1-devel-ea86937

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