From: Frank Chang <frank.chang@sifive.com>

Support the true Zicclsm extension so that we can trap misaligned accesses
when the extension is disabled.

Zicclsm is set to true by default to be backwards compatible with the old
RISC-V QEMU design.

To disable Zicclsm, simply set zicclsm=false, e.g.:
  -cpu rv64,zicclsm=false

QEMU will raise a misaligned load/store exception when executing misaligned
load/store instructions.

Changelog:
  v2:
    * Use (size_memop(size) | mo_endian_env(env)) to calculate MemOp.
    * Use (log2_esz << MO_ASHIFT) to calculate aligment MemOp for
      vector load/store whole register instructions.

Frank Chang (4):
  target/riscv: Add Zicclsm CPU option
  target/riscv: Support raising misaligned exceptions for scalar
    loads/stores
  target/riscv: Support raising misaligned exceptions for vector
    loads/stores
  target/riscv: Expose Zicclsm extension as a CPU property

 target/riscv/cpu.c                      |  4 +-
 target/riscv/cpu_cfg_fields.h.inc       |  2 +
 target/riscv/insn_trans/trans_rvi.c.inc |  6 +++
 target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++--
 target/riscv/vector_helper.c            | 65 +++++++++++++++++++------
 5 files changed, 76 insertions(+), 19 deletions(-)

--
2.43.0