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[PATCH] hw/char: Check interrupt after txctrl register is written

frank.chang@sifive.com posted 1 patch 2 weeks, 3 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260513030503.3665414-1-frank.chang@sifive.com
Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>
hw/char/sifive_uart.c | 1 +
1 file changed, 1 insertion(+)
[PATCH] hw/char: Check interrupt after txctrl register is written
Posted by frank.chang@sifive.com 2 weeks, 3 days ago 
From: Frank Chang <frank.chang@sifive.com>

It's possible that the transmit watermark level (txctrl.txcnt) is
updated when the user writes to txctrl register, which may decrease the
transmit watermark level to less than the number of entries in the
transmit FIFO. In such a case, the interrupt should be raised so we need to
call sifive_uart_update_irq() to check and update interrupt when txctrl
register is written. Otherwise, the interrupt will have to be delayed
until next TX FIFO transmission is processed.

Suggested-by: Chao Liu <chao.liu.zevorn@gmail.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
 hw/char/sifive_uart.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index b4de662d616..b9bbaaef595 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr,
         if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) {
             sifive_uart_trigger_tx_fifo(s);
         }
+        sifive_uart_update_irq(s);
         return;
     case SIFIVE_UART_RXCTRL:
         s->rxctrl = val64;
-- 
2.43.0
Re: [PATCH] hw/char: Check interrupt after txctrl register is written
Posted by Michael Tokarev 4 days, 9 hours ago 
On 13.05.2026 06:05, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> It's possible that the transmit watermark level (txctrl.txcnt) is
> updated when the user writes to txctrl register, which may decrease the
> transmit watermark level to less than the number of entries in the
> transmit FIFO. In such a case, the interrupt should be raised so we need to
> call sifive_uart_update_irq() to check and update interrupt when txctrl
> register is written. Otherwise, the interrupt will have to be delayed
> until next TX FIFO transmission is processed.
> 
> Suggested-by: Chao Liu <chao.liu.zevorn@gmail.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> ---
>   hw/char/sifive_uart.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index b4de662d616..b9bbaaef595 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr,
>           if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) {
>               sifive_uart_trigger_tx_fifo(s);
>           }
> +        sifive_uart_update_irq(s);
>           return;
>       case SIFIVE_UART_RXCTRL:
>           s->rxctrl = val64;


Is this change independent on e6051fa61b9 "hw/char: sifive_uart:
Implement txctrl.txen and rxctrl.rxen", - the one which added the
previous "if SIFIVE_UART_TXEN" code block here?

I mean, should this patch be applied to older qemu stable series too,
namely, 10.0.x (LTS) and 10.2.x, where the above code is not present?
(It applies fine to 11.0.x).

Thanks,

/mjt
Re: [PATCH] hw/char: Check interrupt after txctrl register is written
Posted by Michael Tokarev 4 days, 6 hours ago 
On 26.05.2026 10:00, Michael Tokarev wrote:
> On 13.05.2026 06:05, frank.chang@sifive.com wrote:
>> From: Frank Chang <frank.chang@sifive.com>
>>
>> It's possible that the transmit watermark level (txctrl.txcnt) is
>> updated when the user writes to txctrl register, which may decrease the
>> transmit watermark level to less than the number of entries in the
>> transmit FIFO. In such a case, the interrupt should be raised so we 
>> need to
>> call sifive_uart_update_irq() to check and update interrupt when txctrl
>> register is written. Otherwise, the interrupt will have to be delayed
>> until next TX FIFO transmission is processed.
>>
>> Suggested-by: Chao Liu <chao.liu.zevorn@gmail.com>
>> Signed-off-by: Frank Chang <frank.chang@sifive.com>
>> Reviewed-by: Jim Shu <jim.shu@sifive.com>
>> ---
>>   hw/char/sifive_uart.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
>> index b4de662d616..b9bbaaef595 100644
>> --- a/hw/char/sifive_uart.c
>> +++ b/hw/char/sifive_uart.c
>> @@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr,
>>           if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s- 
>> >tx_fifo)) {
>>               sifive_uart_trigger_tx_fifo(s);
>>           }
>> +        sifive_uart_update_irq(s);
>>           return;
>>       case SIFIVE_UART_RXCTRL:
>>           s->rxctrl = val64;
> 
> 
> Is this change independent on e6051fa61b9 "hw/char: sifive_uart:
> Implement txctrl.txen and rxctrl.rxen", - the one which added the
> previous "if SIFIVE_UART_TXEN" code block here?
> 
> I mean, should this patch be applied to older qemu stable series too,
> namely, 10.0.x (LTS) and 10.2.x, where the above code is not present?
> (It applies fine to 11.0.x).

Or maybe I can just pick up the mentioned change - e6051fa61b9 - to 10.0
and 10.2 too, it shouldn't hurt, and I've less differences to carry :)

Thanks,

/mjt
Re: [PATCH] hw/char: Check interrupt after txctrl register is written
Posted by Frank Chang 4 days, 2 hours ago 
On Tue, May 26, 2026 at 6:44 PM Michael Tokarev <mjt@tls.msk.ru> wrote:

> On 26.05.2026 10:00, Michael Tokarev wrote:
> > On 13.05.2026 06:05, frank.chang@sifive.com wrote:
> >> From: Frank Chang <frank.chang@sifive.com>
> >>
> >> It's possible that the transmit watermark level (txctrl.txcnt) is
> >> updated when the user writes to txctrl register, which may decrease the
> >> transmit watermark level to less than the number of entries in the
> >> transmit FIFO. In such a case, the interrupt should be raised so we
> >> need to
> >> call sifive_uart_update_irq() to check and update interrupt when txctrl
> >> register is written. Otherwise, the interrupt will have to be delayed
> >> until next TX FIFO transmission is processed.
> >>
> >> Suggested-by: Chao Liu <chao.liu.zevorn@gmail.com>
> >> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> >> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> >> ---
> >>   hw/char/sifive_uart.c | 1 +
> >>   1 file changed, 1 insertion(+)
> >>
> >> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> >> index b4de662d616..b9bbaaef595 100644
> >> --- a/hw/char/sifive_uart.c
> >> +++ b/hw/char/sifive_uart.c
> >> @@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr,
> >>           if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s-
> >> >tx_fifo)) {
> >>               sifive_uart_trigger_tx_fifo(s);
> >>           }
> >> +        sifive_uart_update_irq(s);
> >>           return;
> >>       case SIFIVE_UART_RXCTRL:
> >>           s->rxctrl = val64;
> >
> >
> > Is this change independent on e6051fa61b9 "hw/char: sifive_uart:
> > Implement txctrl.txen and rxctrl.rxen", - the one which added the
> > previous "if SIFIVE_UART_TXEN" code block here?
> >
> > I mean, should this patch be applied to older qemu stable series too,
> > namely, 10.0.x (LTS) and 10.2.x, where the above code is not present?
> > (It applies fine to 11.0.x).
>
> Or maybe I can just pick up the mentioned change - e6051fa61b9 - to 10.0
> and 10.2 too, it shouldn't hurt, and I've less differences to carry :)
>

That would be great.
Thanks.

Regard,
Frank Chang


>
> Thanks,
>
> /mjt
>
Re: [PATCH] hw/char: Check interrupt after txctrl register is written
Posted by Michael Tokarev 4 days, 1 hour ago 
On 26.05.2026 17:08, Frank Chang wrote:
> On Tue, May 26, 2026 at 6:44 PM Michael Tokarev <mjt@tls.msk.ru 
> <mailto:mjt@tls.msk.ru>> wrote:

>     Or maybe I can just pick up the mentioned change - e6051fa61b9 - to 10.0
>     and 10.2 too, it shouldn't hurt, and I've less differences to carry :)
> 
> 
> That would be great.

And for 10.0.x, I also picked up 61240e3a06dc622 "hw/char: sifive_uart:
Avoid infinite delay of async xmit function" - which apparently was
missed in there.

Dunno how relevant all this stuff for 10.0.x is.  At any rate, this is
what current debian stable (trixie) is using, and qemu relies on debian
for its CI jobs a lot.

Thanks,

/mjt
Re: [PATCH] hw/char: Check interrupt after txctrl register is written
Posted by Alistair Francis 1 week, 5 days ago 
On Wed, May 13, 2026 at 1:06 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> It's possible that the transmit watermark level (txctrl.txcnt) is
> updated when the user writes to txctrl register, which may decrease the
> transmit watermark level to less than the number of entries in the
> transmit FIFO. In such a case, the interrupt should be raised so we need to
> call sifive_uart_update_irq() to check and update interrupt when txctrl
> register is written. Otherwise, the interrupt will have to be delayed
> until next TX FIFO transmission is processed.
>
> Suggested-by: Chao Liu <chao.liu.zevorn@gmail.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  hw/char/sifive_uart.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index b4de662d616..b9bbaaef595 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr,
>          if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) {
>              sifive_uart_trigger_tx_fifo(s);
>          }
> +        sifive_uart_update_irq(s);
>          return;
>      case SIFIVE_UART_RXCTRL:
>          s->rxctrl = val64;
> --
> 2.43.0
>
>
Re: [PATCH] hw/char: Check interrupt after txctrl register is written
Posted by Alistair Francis 1 week, 5 days ago 
On Wed, May 13, 2026 at 1:06 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> It's possible that the transmit watermark level (txctrl.txcnt) is
> updated when the user writes to txctrl register, which may decrease the
> transmit watermark level to less than the number of entries in the
> transmit FIFO. In such a case, the interrupt should be raised so we need to
> call sifive_uart_update_irq() to check and update interrupt when txctrl
> register is written. Otherwise, the interrupt will have to be delayed
> until next TX FIFO transmission is processed.
>
> Suggested-by: Chao Liu <chao.liu.zevorn@gmail.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/char/sifive_uart.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index b4de662d616..b9bbaaef595 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr,
>          if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) {
>              sifive_uart_trigger_tx_fifo(s);
>          }
> +        sifive_uart_update_irq(s);
>          return;
>      case SIFIVE_UART_RXCTRL:
>          s->rxctrl = val64;
> --
> 2.43.0
>
>

Patchew 2.1-devel-ea86937

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