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[PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes

alistair23@gmail.com posted 1 patch 2 weeks, 3 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260513023859.518484-1-alistair.francis@wdc.com
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
[PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by alistair23@gmail.com 2 weeks, 3 days ago 
From: Alistair Francis <alistair.francis@wdc.com>

Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
Conor and Sebastian as people to help deal with the fixes.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
Conor let me know if it should be a different address

 MAINTAINERS | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 952ed683bb..9626eb1ea9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
 F: tests/tcg/riscv64/test-crc32.S
 
 Microchip PolarFire SoC Icicle Kit
+M: Conor Dooley <conor@kernel.org>
+M: Sebastian Huber <sebastian.huber@embedded-brains.de>
 L: qemu-riscv@nongnu.org
-S: Supported
+S: Odd Fixes
 F: docs/system/riscv/microchip-icicle-kit.rst
 F: hw/riscv/microchip_pfsoc.c
 F: hw/char/mchp_pfsoc_mmuart.c
-- 
2.53.0
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Alistair Francis 1 week, 5 days ago 
On Wed, May 13, 2026 at 12:39 PM <alistair23@gmail.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> Conor and Sebastian as people to help deal with the fixes.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> Conor let me know if it should be a different address
>
>  MAINTAINERS | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 952ed683bb..9626eb1ea9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
>  F: tests/tcg/riscv64/test-crc32.S
>
>  Microchip PolarFire SoC Icicle Kit
> +M: Conor Dooley <conor@kernel.org>
> +M: Sebastian Huber <sebastian.huber@embedded-brains.de>
>  L: qemu-riscv@nongnu.org
> -S: Supported
> +S: Odd Fixes
>  F: docs/system/riscv/microchip-icicle-kit.rst
>  F: hw/riscv/microchip_pfsoc.c
>  F: hw/char/mchp_pfsoc_mmuart.c
> --
> 2.53.0
>
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Conor Dooley 2 weeks, 2 days ago 
On Wed, May 13, 2026 at 12:38:59PM +1000, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> Conor and Sebastian as people to help deal with the fixes.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> Conor let me know if it should be a different address
> 
>  MAINTAINERS | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 952ed683bb..9626eb1ea9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
>  F: tests/tcg/riscv64/test-crc32.S
>  
>  Microchip PolarFire SoC Icicle Kit
> +M: Conor Dooley <conor@kernel.org>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> +M: Sebastian Huber <sebastian.huber@embedded-brains.de>
>  L: qemu-riscv@nongnu.org
> -S: Supported
> +S: Odd Fixes
>  F: docs/system/riscv/microchip-icicle-kit.rst
>  F: hw/riscv/microchip_pfsoc.c
>  F: hw/char/mchp_pfsoc_mmuart.c
> -- 
> 2.53.0
> 
>
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Philippe Mathieu-Daudé 2 weeks, 3 days ago 
On 13/5/26 04:38, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> Conor and Sebastian as people to help deal with the fixes.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> Conor let me know if it should be a different address
> 
>   MAINTAINERS | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 952ed683bb..9626eb1ea9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
>   F: tests/tcg/riscv64/test-crc32.S
>   
>   Microchip PolarFire SoC Icicle Kit
> +M: Conor Dooley <conor@kernel.org>
> +M: Sebastian Huber <sebastian.huber@embedded-brains.de>

Maybe worth having a look at Guenter's following patch for this
machine:
https://github.com/groeck/qemu/commit/1a66d5b4e5fe9
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Conor Dooley 2 weeks, 2 days ago 
On Wed, May 13, 2026 at 08:10:06AM +0200, Philippe Mathieu-Daudé wrote:
> On 13/5/26 04:38, alistair23@gmail.com wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
> > 
> > Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> > Conor and Sebastian as people to help deal with the fixes.
> > 
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > Conor let me know if it should be a different address
> > 
> >   MAINTAINERS | 4 +++-
> >   1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 952ed683bb..9626eb1ea9 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
> >   F: tests/tcg/riscv64/test-crc32.S
> >   Microchip PolarFire SoC Icicle Kit
> > +M: Conor Dooley <conor@kernel.org>
> > +M: Sebastian Huber <sebastian.huber@embedded-brains.de>
> 
> Maybe worth having a look at Guenter's following patch for this
> machine:
> https://github.com/groeck/qemu/commit/1a66d5b4e5fe9

Ye, I can do that. It looks mostly pretty sane, but needs a bit of
cleanup I think before it is really applicable.

Does it matter if the rates the PLLs report are accurate btw? Since
everything here is emulated, it shouldn't matter if the PLLs run say all
at 100 MHz instead of one at 100 and one at 40, right? They're just used
to clock things like i2c or pwm controllers.
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Alistair Francis 2 weeks, 2 days ago 
On Thu, May 14, 2026 at 7:26 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Wed, May 13, 2026 at 08:10:06AM +0200, Philippe Mathieu-Daudé wrote:
> > On 13/5/26 04:38, alistair23@gmail.com wrote:
> > > From: Alistair Francis <alistair.francis@wdc.com>
> > >
> > > Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> > > Conor and Sebastian as people to help deal with the fixes.
> > >
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > ---
> > > Conor let me know if it should be a different address
> > >
> > >   MAINTAINERS | 4 +++-
> > >   1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 952ed683bb..9626eb1ea9 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
> > >   F: tests/tcg/riscv64/test-crc32.S
> > >   Microchip PolarFire SoC Icicle Kit
> > > +M: Conor Dooley <conor@kernel.org>
> > > +M: Sebastian Huber <sebastian.huber@embedded-brains.de>
> >
> > Maybe worth having a look at Guenter's following patch for this
> > machine:
> > https://github.com/groeck/qemu/commit/1a66d5b4e5fe9
>
> Ye, I can do that. It looks mostly pretty sane, but needs a bit of
> cleanup I think before it is really applicable.
>
> Does it matter if the rates the PLLs report are accurate btw? Since

You know the hardware better than us. Generally if it allows the guest
boot and the values are sane then that's probably fine

Alistair

> everything here is emulated, it shouldn't matter if the PLLs run say all
> at 100 MHz instead of one at 100 and one at 40, right? They're just used
> to clock things like i2c or pwm controllers.
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Conor Dooley 2 weeks, 2 days ago 
On Thu, May 14, 2026 at 09:54:43AM +1000, Alistair Francis wrote:
> On Thu, May 14, 2026 at 7:26 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, May 13, 2026 at 08:10:06AM +0200, Philippe Mathieu-Daudé wrote:
> > > On 13/5/26 04:38, alistair23@gmail.com wrote:
> > > > From: Alistair Francis <alistair.francis@wdc.com>
> > > >
> > > > Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> > > > Conor and Sebastian as people to help deal with the fixes.
> > > >
> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > > ---
> > > > Conor let me know if it should be a different address
> > > >
> > > >   MAINTAINERS | 4 +++-
> > > >   1 file changed, 3 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 952ed683bb..9626eb1ea9 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
> > > >   F: tests/tcg/riscv64/test-crc32.S
> > > >   Microchip PolarFire SoC Icicle Kit
> > > > +M: Conor Dooley <conor@kernel.org>
> > > > +M: Sebastian Huber <sebastian.huber@embedded-brains.de>
> > >
> > > Maybe worth having a look at Guenter's following patch for this
> > > machine:
> > > https://github.com/groeck/qemu/commit/1a66d5b4e5fe9
> >
> > Ye, I can do that. It looks mostly pretty sane, but needs a bit of
> > cleanup I think before it is really applicable.
> >
> > Does it matter if the rates the PLLs report are accurate btw? Since
> 
> You know the hardware better than us. Generally if it allows the guest
> boot and the values are sane then that's probably fine

In that case, there's very little that needs doing with it IMO.
Dropping this one line here is probably sufficient:
https://github.com/groeck/qemu/commit/1a66d5b4e5fe9#diff-9d9266aa5117a927eda2de5ec50e77c41664adfbf48599ffaa58c9e7def28d0dR98-R116

I'll test that out and see.

> 
> Alistair
> 
> > everything here is emulated, it shouldn't matter if the PLLs run say all
> > at 100 MHz instead of one at 100 and one at 40, right? They're just used
> > to clock things like i2c or pwm controllers.
>
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Guenter Roeck 2 weeks, 2 days ago 
On 5/13/26 14:26, Conor Dooley wrote:
> On Wed, May 13, 2026 at 08:10:06AM +0200, Philippe Mathieu-Daudé wrote:
>> On 13/5/26 04:38, alistair23@gmail.com wrote:
>>> From: Alistair Francis <alistair.francis@wdc.com>
>>>
>>> Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
>>> Conor and Sebastian as people to help deal with the fixes.
>>>
>>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>>> ---
>>> Conor let me know if it should be a different address
>>>
>>>    MAINTAINERS | 4 +++-
>>>    1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 952ed683bb..9626eb1ea9 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
>>>    F: tests/tcg/riscv64/test-crc32.S
>>>    Microchip PolarFire SoC Icicle Kit
>>> +M: Conor Dooley <conor@kernel.org>
>>> +M: Sebastian Huber <sebastian.huber@embedded-brains.de>
>>
>> Maybe worth having a look at Guenter's following patch for this
>> machine:
>> https://github.com/groeck/qemu/commit/1a66d5b4e5fe9
> 
> Ye, I can do that. It looks mostly pretty sane, but needs a bit of
> cleanup I think before it is really applicable.
> 
> Does it matter if the rates the PLLs report are accurate btw? Since
> everything here is emulated, it shouldn't matter if the PLLs run say all
> at 100 MHz instead of one at 100 and one at 40, right? They're just used
> to clock things like i2c or pwm controllers.


I for my part have no idea, sorry. My only goal was to get rid of the
stack backtraces. I did not explore further.

Guenter
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Sebastian Huber 2 weeks, 3 days ago 
----- Am 13. Mai 2026 um 4:38 schrieb Alistair Francis alistair23@gmail.com:

> From: Alistair Francis <alistair.francis@wdc.com>
> 
> Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> Conor and Sebastian as people to help deal with the fixes.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Thanks, this is fine.

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Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Markus Armbruster 2 weeks, 3 days ago 
Sebastian Huber <sebastian.huber@embedded-brains.de> writes:

> ----- Am 13. Mai 2026 um 4:38 schrieb Alistair Francis alistair23@gmail.com:
>
>> From: Alistair Francis <alistair.francis@wdc.com>
>> 
>> Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
>> Conor and Sebastian as people to help deal with the fixes.
>> 
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>
> Thanks, this is fine.

Can you make it official?  Acked-by: ...

Thanks!
Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes
Posted by Sebastian Huber 2 weeks, 3 days ago 
----- Am 13. Mai 2026 um 7:56 schrieb Markus Armbruster armbru@redhat.com:

> Sebastian Huber <sebastian.huber@embedded-brains.de> writes:
> 
>> ----- Am 13. Mai 2026 um 4:38 schrieb Alistair Francis alistair23@gmail.com:
>>
>>> From: Alistair Francis <alistair.francis@wdc.com>
>>> 
>>> Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
>>> Conor and Sebastian as people to help deal with the fixes.
>>> 
>>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>>
>> Thanks, this is fine.
> 
> Can you make it official?  Acked-by: ...

Acked-by: Sebastian Huber <sebastian.huber@embedded-brains.de>

-- 
VISIT US @ SATELLITE ASIA IN SINGAPORE 20-22 MAY (https://asiatechxsg.com/satelliteasia//): Hall 4, Booth 4K2-4
--
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.huber@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/

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