On 5/11/2026 11:07 PM, Chao Liu wrote:
> Hi Daniel,
> On Mon, May 11, 2026 at 10:28:57AM -0300, Daniel Henrique Barboza wrote:
>> Hi everyone,
>>
>> We have been dealing with two sources of extensions information in
>> target/riscv/cpu.c:
>>
>> - isa_edata_arr[]: an array that we must keep in riscv,isa ordering that
>> also has priv_spec info;
>> - riscv_cpu_* arrays: used to set user properties and set defaults for
>> rv32/rv64, among other users across the code.
>>
>> The main issue here is the info being duplicated across arrays. When
>> adding new extensions we go through a ritual of adding basically the
>> same stuff in both isa_edata_arr[] and riscv_cpu_extensions[]. We can
>> eventually forget to do all steps of that dance, resulting in patch 1.
>>
>> The second issue is a desire for less abstractions. An extension is
>> something that we report in riscv,isa, that might be exposed to users or
>> not, that might be a vendor or an experimental ext. All these
>> distinctions don't require multiple distinct arrays.
>>
>> I also made an effort to start moving away from the 'named features'
>> stuff we have going on. A 'named feature' is just an extension that
>> most of the time isn't exposed to users, most of the time represents
>> innate TCG behavior, and sometimes have a different enable mechanism
>> aside from setting a flag to 'true'. None of that is exclusive to this
>> class of extensions therefore I believe we should move away from it
>> over time.
>>
>> There are more design simplifications I want to do in cpu.c and with CPUs
>> in general, but for now we can enjoy less lines to maintain.
>>
>> Patches based on alistair/riscv-to-apply.next.
>>
> I’m seeing some compile errors after applying these patches on top of commit
> 0844c21f24ca (target/riscv: Update MISA.X for non-standard extensions) from
> alistair/riscv-to-apply.next.
>
> ---
> ../target/riscv/tcg/tcg-cpu.c: In function ‘riscv_cpu_update_misa_x’:
> ../target/riscv/tcg/tcg-cpu.c:1158:11: error: unknown type name ‘RISCVCPUMultiExtConfig’; did you mean ‘RISCVCPUConfig’?
> 1158 | const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;
> | ^~~~~~~~~~~~~~~~~~~~~~
> | RISCVCPUConfig
> ../target/riscv/tcg/tcg-cpu.c:1158:41: error: ‘riscv_cpu_vendor_exts’ undeclared (first use in this function)
> 1158 | const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;
> | ^~~~~~~~~~~~~~~~~~~~~
> ../target/riscv/tcg/tcg-cpu.c:1158:41: note: each undeclared identifier is reported only once for each function it appears in
> ../target/riscv/tcg/tcg-cpu.c:1160:27: error: request for member ‘name’ in something not a structure or union
> 1160 | for (int i = 0; arr[i].name != NULL; i++) {
> | ^
> ../target/riscv/tcg/tcg-cpu.c:1161:43: error: request for member ‘offset’ in something not a structure or union
> 1161 | if (isa_ext_is_enabled(cpu, arr[i].offset)) {
> | ^
> [1658/2250] Compiling C object libqemu-riscv64-softmmu.a.p/target_riscv_vector_helper.c.o
> ninja: build stopped: subcommand failed.
> ---
>
> Maybe try rebasing again and fixing it.
Thanks for catching this up! Guess I somehow missed this change from
Alistair's branch.
I'll send a v2. Thanks,
Daniel
>
> Thanks,
> Chao
>> Daniel Henrique Barboza (13):
>> target/riscv/cpu.c: add xlrbr isa_edata_arr[] entry
>> target/riscv/cpu.c: fix smctr/ssctr isa_edata_arr[] order
>> target/riscv: make riscv-qmp-cmds use isa_data_arr[]
>> target/riscv/tcg: treat all exts equally in
>> cpu_disable_priv_spec_isa_exts
>> target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name()
>> target/riscv/cpu.c: remove riscv_cpu_enable_named_feat()
>> target/riscv: remove riscv_cpu_named_features[]
>> target/riscv/kvm: use isa_edata_arr[] for unavailable props
>> target/riscv/tcg: use isa_edata_arr[] to enable max exts
>> target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque
>> target/riscv: do not set defaults in cpu prop callback
>> target/riscv/tcg: use isa_edata_arr[] to create user props
>> target/riscv/cpu: remove riscv_cpu_* arrays
>>
>> target/riscv/cpu.c | 315 ++++++++++++----------------------
>> target/riscv/cpu.h | 12 +-
>> target/riscv/kvm/kvm-cpu.c | 25 ++-
>> target/riscv/riscv-qmp-cmds.c | 30 +---
>> target/riscv/tcg/tcg-cpu.c | 137 ++++-----------
>> 5 files changed, 153 insertions(+), 366 deletions(-)
>>
>> --
>> 2.43.0
>>