[v6] target/riscv: Implement Smsdid and Smmpt extension

[PATCH v6 0/6] target/riscv: Implement Smsdid and Smmpt extension

LIU Zhiwei posted 6 patches 2 weeks, 5 days ago

Diff against v2 v3 v4 v5
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260511124705.28161-1-zhiwei._5Fliu@linux.alibaba.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/cpu.c                            |  17 +-
target/riscv/cpu.h                            |   9 +-
target/riscv/cpu_bits.h                       |  18 ++
target/riscv/cpu_cfg_fields.h.inc             |   2 +
target/riscv/cpu_helper.c                     | 117 +++++++--
target/riscv/csr.c                            |  95 ++++++++
target/riscv/insn32.decode                    |   2 +
.../riscv/insn_trans/trans_privileged.c.inc   |  30 +++
target/riscv/meson.build                      |   1 +
target/riscv/pmp.h                            |   3 +
target/riscv/riscv_smmpt.c                    | 227 ++++++++++++++++++
target/riscv/riscv_smmpt.h                    |  26 ++
12 files changed, 528 insertions(+), 19 deletions(-)
create mode 100644 target/riscv/riscv_smmpt.c
create mode 100644 target/riscv/riscv_smmpt.h

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[PATCH v6 0/6] target/riscv: Implement Smsdid and Smmpt extension

Posted by LIU Zhiwei 2 weeks, 5 days ago

This patch set introduces support for the RISC-V Smmpt (Supervisor
Memory-tracking and Protection Table) extension
v0.3.4(https://github.com/riscv/riscv-smmtt/releases/tag/v0.3.4).
Smmpt provides a hardware mechanism for fine-grained memory protection,
checked after address translation, which is particularly useful for
supervisor-level sandboxing and security monitoring.

The rfc patch set:
https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html

v5->v6:
    1. Use explicitly bit fields extract instead of mpte_union_t.
    2. Use the same exception behavior for MPT valiation as PMP
       valiation.
    3. Use PAGE_* instead of MPT_ACCESS_* as they have same value.
    4. Use address_space_*_le instead of address_space_* for SMMPT.
    5. Only print SMMPT address check log when SMMPT is enabled.
    6. Add implied rule for SMMPT as it depends on SMSDID.
    7. Rebase to master.

v4->v5:
    1. Rebase to master.
v3->v4:
    1. Add missing review tags.
v2->v3:
    1. Fix build error in patch 2.
    2. Rebase to master.

rfc->v2:
    1. When ext_smmpt is false or BARE mode, make other fields in mmpt
       CSR zero.
    2. Add patch 5 to fix smrnmi ISA string order.
    3. Fix patch 6 smmpt and smsdid ISA string order.
    4. Make smmpt and smsdid experiment extensions.
    5. Add review tags.

LIU Zhiwei (6):
  target/riscv: Add basic definitions and CSRs for SMMPT
  target/riscv: Implement core SMMPT lookup logic
  target/riscv: Integrate SMMPT checks into MMU and TLB fill
  target/riscv: Implement SMMPT fence instructions
  target/riscv: Fix smrnmi isa alphabetical order
  target/riscv: Enable SMMPT extension

 target/riscv/cpu.c                            |  17 +-
 target/riscv/cpu.h                            |   9 +-
 target/riscv/cpu_bits.h                       |  18 ++
 target/riscv/cpu_cfg_fields.h.inc             |   2 +
 target/riscv/cpu_helper.c                     | 117 +++++++--
 target/riscv/csr.c                            |  95 ++++++++
 target/riscv/insn32.decode                    |   2 +
 .../riscv/insn_trans/trans_privileged.c.inc   |  30 +++
 target/riscv/meson.build                      |   1 +
 target/riscv/pmp.h                            |   3 +
 target/riscv/riscv_smmpt.c                    | 227 ++++++++++++++++++
 target/riscv/riscv_smmpt.h                    |  26 ++
 12 files changed, 528 insertions(+), 19 deletions(-)
 create mode 100644 target/riscv/riscv_smmpt.c
 create mode 100644 target/riscv/riscv_smmpt.h

-- 
2.43.0

Re: [PATCH v6 0/6] target/riscv: Implement Smsdid and Smmpt extension

Posted by Alistair Francis 2 weeks, 3 days ago

On Mon, May 11, 2026 at 10:48 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> This patch set introduces support for the RISC-V Smmpt (Supervisor
> Memory-tracking and Protection Table) extension
> v0.3.4(https://github.com/riscv/riscv-smmtt/releases/tag/v0.3.4).

Thanks.

As this is a draft extension we need to support the latest version as
described here [1].

So this will need to support version 0.49

1: https://wiki.qemu.org/Documentation/Platforms/RISCV#RISC-V_Foundation_Extensions

Alistair