On 5/20/26 19:19, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do
> not click links or open attachments unless you recognize the sender
> and know the content is safe.
>
>
> On 20/5/26 16:08, Djordje Todorovic wrote:
>> Hi all,
>>
>> I am wondering, if there is any comment on v9. :)
>>
>> Thanks a lot!
>> Djordje
>>
>>
>> On 5/11/26 10:38, Djordje Todorovic wrote:
>>> Rebase on top of master.
>
> More than a "rebase" comment I was hoping to read what was the
> conclusion on previous versions about wired endianness bits.
>
Yes, sorry, I should have made that clearer in the cover letter.
This was partially addressed in v7 by making `big-endian` a static CPU
configuration option rather than a runtime switch. In v10 I made the
intended model explicit: this series models fixed-endian harts, not a
mixed-endian implementation where software can toggle MBE/SBE/UBE at
runtime.
The reset value of MBE/SBE/UBE is selected from the CPU configuration, and
the bits remain outside the mstatus/mstatush/sstatus writable masks, so
they are effectively hardwired to 0 for the default little-endian CPUs and
to 1 when `big-endian=on`.
I also documented this in the patches and will mention it explicitly in the
v10 cover letter.
>>>
>>> Djordje Todorovic (7):
>>> target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks
>>> target/riscv: Add big-endian CPU configuration field and reset
>>> logic
>>> target/riscv: Implement runtime data endianness via MSTATUS bits
>>> hw/riscv: Make boot code endianness-aware at runtime
>>> target/riscv: Fix page table walk endianness for big-endian harts
>>> target/riscv: Expose big-endian CPU property and add documentation
>>> target/riscv: Add endianness test for RISC-V BE
>>>
>>> docs/system/target-riscv.rst | 24 ++++++
>>> hw/riscv/boot.c | 81
>>> ++++++++++++++++---
>>> include/hw/riscv/boot.h | 1 +
>>> target/riscv/cpu.c | 11 +--
>>> target/riscv/cpu.h | 23 ++++++
>>> target/riscv/cpu_bits.h | 2 +
>>> target/riscv/cpu_cfg_fields.h.inc | 1 +
>>> target/riscv/cpu_helper.c | 28 +++++--
>>> target/riscv/insn_trans/trans_rva.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_rvd.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_rvf.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_rvi.c.inc | 8 +-
>>> target/riscv/insn_trans/trans_rvzacas.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_rvzce.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 +-
>>> target/riscv/insn_trans/trans_xmips.c.inc | 8 +-
>>> target/riscv/insn_trans/trans_xthead.c.inc | 16 ++--
>>> target/riscv/insn_trans/trans_zilsd.c.inc | 4 +-
>>> target/riscv/internals.h | 9 +--
>>> target/riscv/tcg/tcg-cpu.c | 3 +
>>> target/riscv/translate.c | 22 ++---
>>> tests/functional/riscv64/meson.build | 1 +
>>> tests/functional/riscv64/test_endianness.py | 57 +++++++++++++
>>> 25 files changed, 251 insertions(+), 80 deletions(-)
>>> create mode 100644 tests/functional/riscv64/test_endianness.py
>>>
>