target/riscv: add Zvknha as an implied extension for Zvknhb

[PATCH] target/riscv: add Zvknha as an implied extension for Zvknhb

Zishun Yi posted 1 patch 2 weeks ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260511051736.2916225-1-vulab@iscas.ac.cn

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

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[PATCH] target/riscv: add Zvknha as an implied extension for Zvknhb

Posted by Zishun Yi 2 weeks ago

The RISC-V unpriv specification (zvk.adoc) states that "Zvknhb
implies Zvknha". This means that enabling Zvknhb should automatically
enable Zvknha.

Add Zvknha to ZVKNHB_IMPLIED to ensure the dependency is correctly
enforced.

This issue was discovered and reported by SpecHunter, an AI-driven
architecture specification analysis tool.

Link:https://github.com/yizishun/rv-isa-sec/blob/master/output/riscv-isa-manual/pr-2635/qemu.txt
Signed-off-by: Zishun Yi <vulab@iscas.ac.cn>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ce15a17c37de..61430e44020e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2542,7 +2542,7 @@ static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
 static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvknhb),
     .implied_multi_exts = {
-        CPU_CFG_OFFSET(ext_zve64x),
+        CPU_CFG_OFFSET(ext_zve64x), CPU_CFG_OFFSET(ext_zvknha),
 
         RISCV_IMPLIED_EXTS_RULE_END
     },
-- 
2.51.2

Re: [PATCH] target/riscv: add Zvknha as an implied extension for Zvknhb

Posted by Daniel Henrique Barboza 2 weeks ago


On 5/11/2026 2:17 AM, Zishun Yi wrote:
> The RISC-V unpriv specification (zvk.adoc) states that "Zvknhb
> implies Zvknha". This means that enabling Zvknhb should automatically
> enable Zvknha.
> 
> Add Zvknha to ZVKNHB_IMPLIED to ensure the dependency is correctly
> enforced.
> 
> This issue was discovered and reported by SpecHunter, an AI-driven
> architecture specification analysis tool.
> 
> Link:https://github.com/yizishun/rv-isa-sec/blob/master/output/riscv-isa-manual/pr-2635/qemu.txt
> Signed-off-by: Zishun Yi <vulab@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ce15a17c37de..61430e44020e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2542,7 +2542,7 @@ static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
>   static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvknhb),
>       .implied_multi_exts = {
> -        CPU_CFG_OFFSET(ext_zve64x),
> +        CPU_CFG_OFFSET(ext_zve64x), CPU_CFG_OFFSET(ext_zvknha),
>   
>           RISCV_IMPLIED_EXTS_RULE_END
>       },