Hi; here's another arm pullreq. This is big but it's almost
entirely the GICv5 emulation. I did throw in a couple of other
tiny bugfix patches.
thanks
-- PMM
The following changes since commit ee7eb612be8f8886d48c1d0c1f1c65e495138f83:
Merge tag 'single-binary-20260506' of https://github.com/philmd/qemu into staging (2026-05-06 10:45:02 -0400)
are available in the Git repository at:
https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20260507
for you to fetch changes up to 18b664c90085b0d2be9c2ad8c747e00a7a733402:
hw/misc/bcm2835_rng: Specify valid memory access sizes (2026-05-07 15:14:58 +0100)
----------------------------------------------------------------
target-arm queue:
* Initial experimental GICv5 interrupt controller emulation
* target/arm: Report IL=0 for Thumb 16-bit BKPT insn
* hw/misc/bcm2835_rng: Specify valid memory access sizes
----------------------------------------------------------------
Peter Maydell (67):
qom/object: Add object_resolve_and_typecheck()
hw/core: Permit devices to define an array of link properties
hw/intc: Skeleton of GICv5 IRS classes
hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board
hw/intc/arm_gicv5: Implement skeleton code for IRS register frames
hw/intc/arm_gicv5: Add migration blocker
hw/intc/arm_gicv5: Create and validate QOM properties
hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs
hw/intc/arm_gicv5: Define macros for config frame registers
hw/intc/arm_gicv5: Implement IRS ID regs
hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA
hw/intc/arm_gicv5: Implement gicv5_class_name()
hw/intc/arm_gicv5: Add defines for GICv5 architected PPIs
target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns
target/arm: Set up pointer to GICv5 in each CPU
hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR}
hw/intc/arm_gicv5: Cache LPI IST config in a struct
hw/intc/arm_gicv5: Implement gicv5_set_priority()
target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction
hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR
hw/intc/arm_gicv5: Implement remaining set-config functions
target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config
hw/intc/arm_gicv5: Create backing state for SPIs
hw/intc/arm_gicv5: Make gicv5_set_* update SPI state
hw/intc/arm_gicv5: Implement gicv5_request_config()
target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1
hw/intc/arm_gicv5: Implement IRS_SPI_{SELR, STATUSR, CFGR, DOMAINR}
hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events
hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1
hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR
hw/intc/arm_gicv5: Implement IRS_PE_{CR0, SELR, STATUSR}
hw/intc/arm_gicv5: Implement CoreSight ID registers
hw/intc/arm_gicv5: Cache pending LPIs in a hash table
target/arm: GICv5 cpuif: Implement ICC_IAFFIDR_EL1
target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1
target/arm: GICv5 cpuif: Implement GICv5 PPI active set/clear registers
target/arm: GICv5 cpuif: Implement PPI handling mode register
target/arm: GICv5 cpuif: Implement PPI pending status registers
target/arm: GICv5 cpuif: Implement PPI enable register
target/arm: GICv5 cpuif: Implement PPI priority registers
target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1
target/arm: GICv5 cpuif: Calculate the highest priority PPI
hw/intc/arm_gicv5: Calculate HPPI in the IRS
target/arm: GICv5 cpuif: Implement ICC_CR0_EL1
target/arm: GICv5 cpuif: Implement ICC_PCR_EL1
target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1
hw/intc/arm_gicv5: Implement Activate command
target/arm: GICv5 cpuif: Implement GICR CDIA command
target/arm: GICv5 cpuif: Implement GIC CDEOI
hw/intc/arm_gicv5: Implement Deactivate command
target/arm: GICv5 cpuif: Implement GIC CDDI
target/arm: GICv5 cpuif: Signal IRQ or FIQ
target/arm: Connect internal interrupt sources up as GICv5 PPIs
target/arm: Add has_gcie property to enable FEAT_GCIE
hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif
hw/arm/virt: Remember CPU phandles rather than looking them up by name
hw/arm/virt: Move MSI controller creation out of create_gic()
hw/arm/virt: Pull "wire CPU interrupts" out of create_gic()
hw/arm/virt: Split GICv2 and GICv3/4 creation
hw/arm/virt: Create and connect GICv5
hw/arm/virt: Advertise GICv5 in the DTB
hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs
hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB
hw/arm/virt: Enable GICv5 CPU interface when using GICv5
hw/arm/virt: Allow user to select GICv5
target/arm: Report IL=0 for Thumb 16-bit BKPT insn
hw/misc/bcm2835_rng: Specify valid memory access sizes
docs/system/arm/virt.rst | 19 +
hw/arm/Kconfig | 1 +
hw/arm/virt.c | 527 +++++++---
hw/core/qdev-properties.c | 78 ++
hw/intc/Kconfig | 5 +
hw/intc/arm_gicv3.c | 2 +-
hw/intc/arm_gicv3_cpuif.c | 14 +-
hw/intc/arm_gicv5.c | 1962 ++++++++++++++++++++++++++++++++++++
hw/intc/arm_gicv5_common.c | 215 ++++
hw/intc/gicv3_internal.h | 2 +-
hw/intc/meson.build | 4 +
hw/intc/trace-events | 23 +
hw/misc/bcm2835_rng.c | 4 +
include/hw/arm/fdt.h | 10 +
include/hw/arm/virt.h | 15 +
include/hw/core/qdev-properties.h | 41 +
include/hw/intc/arm_gicv5.h | 51 +
include/hw/intc/arm_gicv5_common.h | 247 +++++
include/hw/intc/arm_gicv5_stream.h | 228 +++++
include/hw/intc/arm_gicv5_types.h | 110 ++
include/qom/object.h | 17 +
meson.build | 1 +
qom/object.c | 41 +-
target/arm/cpregs-pmu.c | 9 +-
target/arm/cpu-features.h | 6 +
target/arm/cpu.c | 62 ++
target/arm/cpu.h | 28 +
target/arm/helper.c | 21 +
target/arm/internals.h | 9 +
target/arm/tcg-stubs.c | 4 +
target/arm/tcg/gicv5-cpuif.c | 952 +++++++++++++++++
target/arm/tcg/meson.build | 1 +
target/arm/tcg/trace-events | 11 +
target/arm/tcg/trace.h | 1 +
target/arm/tcg/translate.c | 2 +-
35 files changed, 4564 insertions(+), 159 deletions(-)
create mode 100644 hw/intc/arm_gicv5.c
create mode 100644 hw/intc/arm_gicv5_common.c
create mode 100644 include/hw/intc/arm_gicv5.h
create mode 100644 include/hw/intc/arm_gicv5_common.h
create mode 100644 include/hw/intc/arm_gicv5_stream.h
create mode 100644 include/hw/intc/arm_gicv5_types.h
create mode 100644 target/arm/tcg/gicv5-cpuif.c
create mode 100644 target/arm/tcg/trace-events
create mode 100644 target/arm/tcg/trace.h