disas/riscv.c | 9 ++ target/riscv/cpu.c | 15 ++- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/helper.h | 12 +++ target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvbf16.c.inc | 32 +++++-- target/riscv/insn_trans/trans_rvofp8.c.inc | 105 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++ target/riscv/tcg/tcg-cpu.c | 5 + target/riscv/translate.c | 1 + target/riscv/vector_helper.c | 104 +++++++++++++++++++- 11 files changed, 315 insertions(+), 13 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc
This patchset adds support for the RISC-V Zvfofp8min isa extension that
provide conversion operations for OCP FP formats.
* riscv-isa-manual tag: https://github.com/riscv/riscv-isa-manual/releases/tag/zvfofp8min-0.9
Zvfofp8min (v0.9):
The Zvfofp8min extension provides minimal vector conversion support
for OFP8 formats. It requires the Zve32f extension and leverages the
altfmt field in the VTYPE CSR (introduced by Zvfbfa) to select between
E4M3 (altfmt=0) and E5M2 (altfmt=1) formats.
- Canonical NaN for both E4M3 and E5M2 is 0x7f
- All NaNs are treated as quiet NaNs
Instructions added/extended:
- vfwcvtbf16.f.f.v: OFP8 to BF16 widening conversion
- vfncvtbf16.f.f.w: BF16 to OFP8 narrowing conversion
- vfncvtbf16.sat.f.f.w: BF16 to OFP8 with saturation (new)
- vfncvt.f.f.q: FP32 to OFP8 quad-narrowing conversion (new)
- vfncvt.sat.f.f.q: FP32 to OFP8 with saturation (new)
Changes in v5
- Drop Zvfofp4min which is not going through the RVIA ratification
process yet.
- Fix typos.
- Rebase on riscv-to-apply.next (commit bf76a00)
Chagnes in v4
- Rebase on riscv-to-apply.next (commit 21101a7)
- Remove the softfloat library related patches (Thanks for RH's help to
split this part)
- Add missing illegal ALTFMT SEW pattern checking for Zvfofp8min in
patch 4 (target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16
conversion for Zvfofp8min extension)
Changes in v3
- Add floatN_nan_is_snan to simply the quiet/signaling NaN checking flow
in patch 2 & 3
- Add patch 4 to fix pseudo-NaN handling in FPATAN/FYL2XP1/FYL2X helpers
Changes in v2
- Merged v1 patch 2 & 3 to v2 patch 3, v1 patch 4 & 5 to v2 patch 4
- Added new v2 patch 2 to refactor the IEEE format NaN classification
functions (float16, bfloat16, float32, float64) to use internal helper
functions, reducing code duplication and improving maintainability.
The OCP FP8 NaN classification functions follow the same pattern.
- Refactored softfloat implementation to use capability-based FloatFmt
flags (no_infinity, limited_nan, overflow_raises_invalid, normal_frac_max)
instead of monolithic flags
- Removed ocp_fp8e5m2_no_signal_nan and ocp_fp8_same_canonical_nan flags
from float_status; now using local float_status with no_signaling_nans
and default_nan_pattern for RISC-V Zvfofp8min instructions
- Rebased on latest riscv-to-apply.next with zvfbfa v3 patchset
v4: <20260304134006.2908449-1-max.chou@sifive.com>
v3: <20260204051756.667397-1-max.chou@sifive.com>
v2: <20260127063723.442734-1-max.chou@sifive.com>
v1: <20260108151650.16329-1-max.chou@sifive.com>
References
* OCP FP8 specification:
https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1
Max Chou (9):
target/riscv: rvv: Fix NOP_UU_B vs2 width
target/riscv: Add cfg property for Zvfofp8min extension
target/riscv: Add implied rules for Zvfofp8min extension
target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16
conversion for Zvfofp8min extension
target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8
conversion for Zvfofp8min extension
target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min
extension
target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions
for Zvfofp8min extension
target/riscv: Expose Zvfofp8min property
disas/riscv: Add support of Zvfofp8min extension
disas/riscv.c | 9 ++
target/riscv/cpu.c | 15 ++-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/helper.h | 12 +++
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvbf16.c.inc | 32 +++++--
target/riscv/insn_trans/trans_rvofp8.c.inc | 105 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++
target/riscv/tcg/tcg-cpu.c | 5 +
target/riscv/translate.c | 1 +
target/riscv/vector_helper.c | 104 +++++++++++++++++++-
11 files changed, 315 insertions(+), 13 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc
--
2.52.0
Gental ping. On 2026-04-27 14:09, Max Chou wrote: > This patchset adds support for the RISC-V Zvfofp8min isa extension that > provide conversion operations for OCP FP formats. > > * riscv-isa-manual tag: https://github.com/riscv/riscv-isa-manual/releases/tag/zvfofp8min-0.9 > > Zvfofp8min (v0.9): > The Zvfofp8min extension provides minimal vector conversion support > for OFP8 formats. It requires the Zve32f extension and leverages the > altfmt field in the VTYPE CSR (introduced by Zvfbfa) to select between > E4M3 (altfmt=0) and E5M2 (altfmt=1) formats. > - Canonical NaN for both E4M3 and E5M2 is 0x7f > - All NaNs are treated as quiet NaNs > Instructions added/extended: > - vfwcvtbf16.f.f.v: OFP8 to BF16 widening conversion > - vfncvtbf16.f.f.w: BF16 to OFP8 narrowing conversion > - vfncvtbf16.sat.f.f.w: BF16 to OFP8 with saturation (new) > - vfncvt.f.f.q: FP32 to OFP8 quad-narrowing conversion (new) > - vfncvt.sat.f.f.q: FP32 to OFP8 with saturation (new) > > Changes in v5 > - Drop Zvfofp4min which is not going through the RVIA ratification > process yet. > - Fix typos. > - Rebase on riscv-to-apply.next (commit bf76a00) > > Chagnes in v4 > - Rebase on riscv-to-apply.next (commit 21101a7) > - Remove the softfloat library related patches (Thanks for RH's help to > split this part) > - Add missing illegal ALTFMT SEW pattern checking for Zvfofp8min in > patch 4 (target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 > conversion for Zvfofp8min extension) > > Changes in v3 > - Add floatN_nan_is_snan to simply the quiet/signaling NaN checking flow > in patch 2 & 3 > - Add patch 4 to fix pseudo-NaN handling in FPATAN/FYL2XP1/FYL2X helpers > > Changes in v2 > - Merged v1 patch 2 & 3 to v2 patch 3, v1 patch 4 & 5 to v2 patch 4 > - Added new v2 patch 2 to refactor the IEEE format NaN classification > functions (float16, bfloat16, float32, float64) to use internal helper > functions, reducing code duplication and improving maintainability. > The OCP FP8 NaN classification functions follow the same pattern. > - Refactored softfloat implementation to use capability-based FloatFmt > flags (no_infinity, limited_nan, overflow_raises_invalid, normal_frac_max) > instead of monolithic flags > - Removed ocp_fp8e5m2_no_signal_nan and ocp_fp8_same_canonical_nan flags > from float_status; now using local float_status with no_signaling_nans > and default_nan_pattern for RISC-V Zvfofp8min instructions > - Rebased on latest riscv-to-apply.next with zvfbfa v3 patchset > > v4: <20260304134006.2908449-1-max.chou@sifive.com> > v3: <20260204051756.667397-1-max.chou@sifive.com> > v2: <20260127063723.442734-1-max.chou@sifive.com> > v1: <20260108151650.16329-1-max.chou@sifive.com> > > References > * OCP FP8 specification: > https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1 > > > Max Chou (9): > target/riscv: rvv: Fix NOP_UU_B vs2 width > target/riscv: Add cfg property for Zvfofp8min extension > target/riscv: Add implied rules for Zvfofp8min extension > target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 > conversion for Zvfofp8min extension > target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8 > conversion for Zvfofp8min extension > target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min > extension > target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions > for Zvfofp8min extension > target/riscv: Expose Zvfofp8min property > disas/riscv: Add support of Zvfofp8min extension > > disas/riscv.c | 9 ++ > target/riscv/cpu.c | 15 ++- > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/helper.h | 12 +++ > target/riscv/insn32.decode | 5 + > target/riscv/insn_trans/trans_rvbf16.c.inc | 32 +++++-- > target/riscv/insn_trans/trans_rvofp8.c.inc | 105 +++++++++++++++++++++ > target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++ > target/riscv/tcg/tcg-cpu.c | 5 + > target/riscv/translate.c | 1 + > target/riscv/vector_helper.c | 104 +++++++++++++++++++- > 11 files changed, 315 insertions(+), 13 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc > > -- > 2.52.0 >
Hi Max! On 5/26/2026 11:00 PM, Max Chou wrote: > Gental ping. I believe we'll need a resend with a rebase due to changes done in the last PR, in particular a change I did where I removed the riscv_cpu_* arrays. In other words: we don't need patch 8 anymore. Thanks, Daniel > > On 2026-04-27 14:09, Max Chou wrote: >> This patchset adds support for the RISC-V Zvfofp8min isa extension that >> provide conversion operations for OCP FP formats. >> >> * riscv-isa-manual tag: https://github.com/riscv/riscv-isa-manual/releases/tag/zvfofp8min-0.9 >> >> Zvfofp8min (v0.9): >> The Zvfofp8min extension provides minimal vector conversion support >> for OFP8 formats. It requires the Zve32f extension and leverages the >> altfmt field in the VTYPE CSR (introduced by Zvfbfa) to select between >> E4M3 (altfmt=0) and E5M2 (altfmt=1) formats. >> - Canonical NaN for both E4M3 and E5M2 is 0x7f >> - All NaNs are treated as quiet NaNs >> Instructions added/extended: >> - vfwcvtbf16.f.f.v: OFP8 to BF16 widening conversion >> - vfncvtbf16.f.f.w: BF16 to OFP8 narrowing conversion >> - vfncvtbf16.sat.f.f.w: BF16 to OFP8 with saturation (new) >> - vfncvt.f.f.q: FP32 to OFP8 quad-narrowing conversion (new) >> - vfncvt.sat.f.f.q: FP32 to OFP8 with saturation (new) >> >> Changes in v5 >> - Drop Zvfofp4min which is not going through the RVIA ratification >> process yet. >> - Fix typos. >> - Rebase on riscv-to-apply.next (commit bf76a00) >> >> Chagnes in v4 >> - Rebase on riscv-to-apply.next (commit 21101a7) >> - Remove the softfloat library related patches (Thanks for RH's help to >> split this part) >> - Add missing illegal ALTFMT SEW pattern checking for Zvfofp8min in >> patch 4 (target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 >> conversion for Zvfofp8min extension) >> >> Changes in v3 >> - Add floatN_nan_is_snan to simply the quiet/signaling NaN checking flow >> in patch 2 & 3 >> - Add patch 4 to fix pseudo-NaN handling in FPATAN/FYL2XP1/FYL2X helpers >> >> Changes in v2 >> - Merged v1 patch 2 & 3 to v2 patch 3, v1 patch 4 & 5 to v2 patch 4 >> - Added new v2 patch 2 to refactor the IEEE format NaN classification >> functions (float16, bfloat16, float32, float64) to use internal helper >> functions, reducing code duplication and improving maintainability. >> The OCP FP8 NaN classification functions follow the same pattern. >> - Refactored softfloat implementation to use capability-based FloatFmt >> flags (no_infinity, limited_nan, overflow_raises_invalid, normal_frac_max) >> instead of monolithic flags >> - Removed ocp_fp8e5m2_no_signal_nan and ocp_fp8_same_canonical_nan flags >> from float_status; now using local float_status with no_signaling_nans >> and default_nan_pattern for RISC-V Zvfofp8min instructions >> - Rebased on latest riscv-to-apply.next with zvfbfa v3 patchset >> >> v4: <20260304134006.2908449-1-max.chou@sifive.com> >> v3: <20260204051756.667397-1-max.chou@sifive.com> >> v2: <20260127063723.442734-1-max.chou@sifive.com> >> v1: <20260108151650.16329-1-max.chou@sifive.com> >> >> References >> * OCP FP8 specification: >> https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1 >> >> >> Max Chou (9): >> target/riscv: rvv: Fix NOP_UU_B vs2 width >> target/riscv: Add cfg property for Zvfofp8min extension >> target/riscv: Add implied rules for Zvfofp8min extension >> target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 >> conversion for Zvfofp8min extension >> target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8 >> conversion for Zvfofp8min extension >> target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min >> extension >> target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions >> for Zvfofp8min extension >> target/riscv: Expose Zvfofp8min property >> disas/riscv: Add support of Zvfofp8min extension >> >> disas/riscv.c | 9 ++ >> target/riscv/cpu.c | 15 ++- >> target/riscv/cpu_cfg_fields.h.inc | 1 + >> target/riscv/helper.h | 12 +++ >> target/riscv/insn32.decode | 5 + >> target/riscv/insn_trans/trans_rvbf16.c.inc | 32 +++++-- >> target/riscv/insn_trans/trans_rvofp8.c.inc | 105 +++++++++++++++++++++ >> target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++ >> target/riscv/tcg/tcg-cpu.c | 5 + >> target/riscv/translate.c | 1 + >> target/riscv/vector_helper.c | 104 +++++++++++++++++++- >> 11 files changed, 315 insertions(+), 13 deletions(-) >> create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc >> >> -- >> 2.52.0 >>
Hi Daniel, Thank you for the information. I'll rebase this patchset and send out v6 Thank, rnax On 2026-05-27 10:03, Daniel Henrique Barboza wrote: > Hi Max! > > On 5/26/2026 11:00 PM, Max Chou wrote: > > Gental ping. > > > I believe we'll need a resend with a rebase due to changes done in the > last PR, in particular a change I did where I removed the riscv_cpu_* > arrays. In other words: we don't need patch 8 anymore. > > > Thanks, > Daniel > > > > > On 2026-04-27 14:09, Max Chou wrote: > > > This patchset adds support for the RISC-V Zvfofp8min isa extension that > > > provide conversion operations for OCP FP formats. > > > > > > * riscv-isa-manual tag: https://github.com/riscv/riscv-isa-manual/releases/tag/zvfofp8min-0.9 > > > > > > Zvfofp8min (v0.9): > > > The Zvfofp8min extension provides minimal vector conversion support > > > for OFP8 formats. It requires the Zve32f extension and leverages the > > > altfmt field in the VTYPE CSR (introduced by Zvfbfa) to select between > > > E4M3 (altfmt=0) and E5M2 (altfmt=1) formats. > > > - Canonical NaN for both E4M3 and E5M2 is 0x7f > > > - All NaNs are treated as quiet NaNs > > > Instructions added/extended: > > > - vfwcvtbf16.f.f.v: OFP8 to BF16 widening conversion > > > - vfncvtbf16.f.f.w: BF16 to OFP8 narrowing conversion > > > - vfncvtbf16.sat.f.f.w: BF16 to OFP8 with saturation (new) > > > - vfncvt.f.f.q: FP32 to OFP8 quad-narrowing conversion (new) > > > - vfncvt.sat.f.f.q: FP32 to OFP8 with saturation (new) > > > > > > Changes in v5 > > > - Drop Zvfofp4min which is not going through the RVIA ratification > > > process yet. > > > - Fix typos. > > > - Rebase on riscv-to-apply.next (commit bf76a00) > > > > > > Chagnes in v4 > > > - Rebase on riscv-to-apply.next (commit 21101a7) > > > - Remove the softfloat library related patches (Thanks for RH's help to > > > split this part) > > > - Add missing illegal ALTFMT SEW pattern checking for Zvfofp8min in > > > patch 4 (target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 > > > conversion for Zvfofp8min extension) > > > > > > Changes in v3 > > > - Add floatN_nan_is_snan to simply the quiet/signaling NaN checking flow > > > in patch 2 & 3 > > > - Add patch 4 to fix pseudo-NaN handling in FPATAN/FYL2XP1/FYL2X helpers > > > > > > Changes in v2 > > > - Merged v1 patch 2 & 3 to v2 patch 3, v1 patch 4 & 5 to v2 patch 4 > > > - Added new v2 patch 2 to refactor the IEEE format NaN classification > > > functions (float16, bfloat16, float32, float64) to use internal helper > > > functions, reducing code duplication and improving maintainability. > > > The OCP FP8 NaN classification functions follow the same pattern. > > > - Refactored softfloat implementation to use capability-based FloatFmt > > > flags (no_infinity, limited_nan, overflow_raises_invalid, normal_frac_max) > > > instead of monolithic flags > > > - Removed ocp_fp8e5m2_no_signal_nan and ocp_fp8_same_canonical_nan flags > > > from float_status; now using local float_status with no_signaling_nans > > > and default_nan_pattern for RISC-V Zvfofp8min instructions > > > - Rebased on latest riscv-to-apply.next with zvfbfa v3 patchset > > > > > > v4: <20260304134006.2908449-1-max.chou@sifive.com> > > > v3: <20260204051756.667397-1-max.chou@sifive.com> > > > v2: <20260127063723.442734-1-max.chou@sifive.com> > > > v1: <20260108151650.16329-1-max.chou@sifive.com> > > > > > > References > > > * OCP FP8 specification: > > > https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1 > > > > > > > > > Max Chou (9): > > > target/riscv: rvv: Fix NOP_UU_B vs2 width > > > target/riscv: Add cfg property for Zvfofp8min extension > > > target/riscv: Add implied rules for Zvfofp8min extension > > > target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 > > > conversion for Zvfofp8min extension > > > target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8 > > > conversion for Zvfofp8min extension > > > target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min > > > extension > > > target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions > > > for Zvfofp8min extension > > > target/riscv: Expose Zvfofp8min property > > > disas/riscv: Add support of Zvfofp8min extension > > > > > > disas/riscv.c | 9 ++ > > > target/riscv/cpu.c | 15 ++- > > > target/riscv/cpu_cfg_fields.h.inc | 1 + > > > target/riscv/helper.h | 12 +++ > > > target/riscv/insn32.decode | 5 + > > > target/riscv/insn_trans/trans_rvbf16.c.inc | 32 +++++-- > > > target/riscv/insn_trans/trans_rvofp8.c.inc | 105 +++++++++++++++++++++ > > > target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++ > > > target/riscv/tcg/tcg-cpu.c | 5 + > > > target/riscv/translate.c | 1 + > > > target/riscv/vector_helper.c | 104 +++++++++++++++++++- > > > 11 files changed, 315 insertions(+), 13 deletions(-) > > > create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc > > > > > > -- > > > 2.52.0 > > > >
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