[v1] target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL

[PATCH 0/1] target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL

Abhigyan Kumar posted 1 patch 4 weeks ago

Diff against v1
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git fetch https://github.com/patchew-project/qemu tags/patchew/20260427060849.749179-1-314abh@gmail.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/csr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

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[PATCH 0/1] target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL

Posted by Abhigyan Kumar 4 weeks ago

This patch ensures that the read-only zero bit (i.e. the 11th bit) of
medeleg remains zero, adhering the RISC-V specification.

I'm a first time contributor. I was a bit confused when it came to
writing tests for this. However, I did debug it via gdb myself and
confirmed the patch works. I would like to seek guidance on how can I
add a test for CSR issues like this -- or if it's even required in this
specific case.

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3438

Abhigyan Kumar (1):
  target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL

 target/riscv/csr.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

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2.54.0