v4 addresses the review comments from Phil and picks up some r-b from
Chao, Phil and Alistair. Thanks for the reviews.

  - Describe PCIe mappings separately from the MemMapEntry table so
    the mappings aren't mixed with fixed hardware addresses. The
    mappings used are changed too, and the XXX comment and check was
    dropped
  - Move temperature sensor from bus 0 to bus 4 and use ti,tmp105
    compatible instead of national,lm75 to match the QEMU model name 
  - Add i2c_get_bus() to do bounds checking on getting i2c buses
  - Make halting payload const 
  - Don't remove rootfs in functional test, the test framework handles
    cleanup
  - Rename Svadu patch to  to better describe what it does
  - Other minor cleanups

v3: https://lore.kernel.org/qemu-devel/20260421053140.752059-1-joel@jms.id.au/

Original cover letter:

Introducing Tenstorrent Atlantis!

 The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
 and CoreLab Technology. It is based on the Atlantis SoC, which includes
 the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.

 The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
 RISC-V CPU.

This initial series adds the base machine support including:

 - AIA (Advanced Interrupt Architecture) support
 - PCIe controller and DesignWare I2C integration
 - Serial console and device tree generation
 - Functional tests for OpenSBI+Linux boot

Chris Rauer (1):
  hw/i2c: Add designware i2c controller

Joel Stanley (5):
  hw/riscv/virt: Move AIA initialisation to helper file
  hw/riscv/aia: Provide number of irq sources
  hw/riscv: Add Tenstorrent Atlantis machine
  hw/riscv/atlantis: Integrate i2c buses
  hw/riscv/atlantis: Add some i2c peripherals

Nicholas Piggin (7):
  hw/riscv/boot: Describe discontiguous memory in boot_info
  hw/riscv/boot: Account for discontiguous memory when loading firmware
  hw/riscv/boot: Provide a simple halting payload
  target/riscv: tt-ascalon: Enable Zkr extension
  target/riscv: tt-ascalon: Enable Svadu by removing Svade
  hw/riscv/atlantis: Add PCIe controller
  tests/functional/riscv64: Add tt-atlantis tests

 MAINTAINERS                                  |  20 +
 docs/system/riscv/tt_atlantis.rst            |  38 +
 docs/system/target-riscv.rst                 |   1 +
 hw/riscv/aia.h                               |  25 +
 include/hw/i2c/designware_i2c.h              | 101 ++
 include/hw/riscv/boot.h                      |  13 +-
 include/hw/riscv/tt_atlantis.h               |  86 ++
 include/hw/riscv/virt.h                      |   2 +-
 hw/i2c/designware_i2c.c                      | 817 ++++++++++++++++
 hw/riscv/aia.c                               |  93 ++
 hw/riscv/boot.c                              |  45 +-
 hw/riscv/microchip_pfsoc.c                   |   6 +-
 hw/riscv/opentitan.c                         |   6 +-
 hw/riscv/shakti_c.c                          |   6 +-
 hw/riscv/sifive_u.c                          |   6 +-
 hw/riscv/spike.c                             |   6 +-
 hw/riscv/tt_atlantis.c                       | 944 +++++++++++++++++++
 hw/riscv/virt-acpi-build.c                   |  27 +-
 hw/riscv/virt.c                              |  96 +-
 hw/riscv/xiangshan_kmh.c                     |   6 +-
 target/riscv/cpu.c                           |   2 +-
 hw/i2c/Kconfig                               |   4 +
 hw/i2c/meson.build                           |   1 +
 hw/i2c/trace-events                          |   4 +
 hw/riscv/Kconfig                             |  19 +
 hw/riscv/meson.build                         |   3 +-
 tests/functional/riscv64/meson.build         |   1 +
 tests/functional/riscv64/test_opensbi.py     |   4 +
 tests/functional/riscv64/test_tt_atlantis.py |  59 ++
 29 files changed, 2333 insertions(+), 108 deletions(-)
 create mode 100644 docs/system/riscv/tt_atlantis.rst
 create mode 100644 hw/riscv/aia.h
 create mode 100644 include/hw/i2c/designware_i2c.h
 create mode 100644 include/hw/riscv/tt_atlantis.h
 create mode 100644 hw/i2c/designware_i2c.c
 create mode 100644 hw/riscv/aia.c
 create mode 100644 hw/riscv/tt_atlantis.c
 create mode 100755 tests/functional/riscv64/test_tt_atlantis.py

-- 
2.47.3