[v4] Set MISA.[C|X] based on the selected extensions

[PATCH v4 0/2] Set MISA.[C|X] based on the selected extensions

frank.chang@sifive.com posted 2 patches 1 month ago

Diff against v2 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260424050509.3935180-1-frank.chang@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/cpu.h         |  1 +
target/riscv/tcg/tcg-cpu.c | 54 ++++++++++++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)

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[PATCH v4 0/2] Set MISA.[C|X] based on the selected extensions

Posted by frank.chang@sifive.com 1 month ago

From: Frank Chang <frank.chang@sifive.com>

MISA.C and MISA.X should be set when the following extensions are
selected:

MISA.C:
  * Zca and not F.
  * Zca, Zcf and F (but not D) is specified (RV32 only).
  * Zca, Zcf and Zcd if D is specified (RV32 only).
  * Zca, Zcd if D is specified (RV64 only)

MISA.X:
  * When there are any non-standard extensions enabled.

This patchset sets MISA.[C|X] bits based on the selected extensions.

Changelog:
  * v4: Warn user if user disables RVC but RVC is mandated by Zca/Zcf/Zcd
        extensions.
  * v3: Rebase to the latest to-apply.next branch.
  * v2: Fix the missing parentheses bug.

Frank Chang (2):
  target/riscv: Update MISA.C for Zc* extensions
  target/riscv: Update MISA.X for non-standard extensions

 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.c | 54 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+)

--
2.43.0

Re: [PATCH v4 0/2] Set MISA.[C|X] based on the selected extensions

Posted by Alistair Francis 4 weeks, 1 day ago

On Fri, Apr 24, 2026 at 3:07 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> MISA.C and MISA.X should be set when the following extensions are
> selected:
>
> MISA.C:
>   * Zca and not F.
>   * Zca, Zcf and F (but not D) is specified (RV32 only).
>   * Zca, Zcf and Zcd if D is specified (RV32 only).
>   * Zca, Zcd if D is specified (RV64 only)
>
> MISA.X:
>   * When there are any non-standard extensions enabled.
>
> This patchset sets MISA.[C|X] bits based on the selected extensions.
>
> Changelog:
>   * v4: Warn user if user disables RVC but RVC is mandated by Zca/Zcf/Zcd
>         extensions.
>   * v3: Rebase to the latest to-apply.next branch.
>   * v2: Fix the missing parentheses bug.
>
> Frank Chang (2):
>   target/riscv: Update MISA.C for Zc* extensions
>   target/riscv: Update MISA.X for non-standard extensions

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.h         |  1 +
>  target/riscv/tcg/tcg-cpu.c | 54 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 55 insertions(+)
>
> --
> 2.43.0
>
>