Changes for v2:
- Implement FEAT_LUT, a prerequisite missed in v1.
Sorted the final "enable FEAT_FP8" after "enable FEAT_LUT".
And I should have mentioned before: this needs a firmware update for
tests/functional/aarch64/test_rme_virt.py
tests/functional/aarch64/test_rme_sbsaref.py
for the new cpu state in FEAT_FPMR, as the kernel we run tries to use
the advertised FPMR and we get a trap to EL3. Once again I wish TF-A
would filter the reported ID registers to match the features for which
it is configured.
Pierrick, are you happy to continue hosting these images, or should we
nominate a Linaro host for these?
r~
Cc: pierrick.bouvier@oss.qualcomm.com
Cc: alex.bennee@linaro.org
Richard Henderson (40):
target/arm: Implement ID_AA64ISAR3
target/arm: Implement FEAT_FAMINMAX for AdvSIMD
target/arm: Implement FEAT_FAMINMAX for SME
target/arm: Implement FEAT_FAMINMAX for SVE
target/arm: Enable FEAT_FAMINMAX for -cpu max
target/arm: Update SCR bits for Arm ARM M.a.a
target/arm: Update HCRX bits for Arm ARM M.a.a
target/arm: Introduce FPMR
target/arm: Update SCTLR bits for FEAT_FPMR
target/arm: Enable EnFPM bits for FEAT_FPMR
target/arm: Clear FPMR on ResetSVEState
target/arm: Add FPMR_EL to TBFLAGS
target/arm: Trap direct acceses to FPMR
target/arm: Enable FEAT_FPMR for -cpu max
target/arm: Implement ID_AA64FPFR0
target/arm: Add isar_feature_aa64_f8cvt
target/arm: Implement FSCALE for AdvSIMD
target/arm: Implement FSCALE for SME
fpu: Add scalbn argument to fp8 conversion routines
fpu: Add conversions between float16 and float8 formats
target/arm: Split vector-type.h from cpu.h
target/arm: Move vectors_overlap to vec_internal.h
target/arm: Implement BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 for AdvSIMD
target/arm: Implement BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT for SVE
target/arm: Rename SME BFCVT patterns to BFCVT_hs
target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME
target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD
target/arm: Implement F1CVT, F1CVTLT, F2CVT, F2CVTLT for SVE
target/arm: Implement F1CVT, F1CVTL, F2CVT, F2CVTL for SME
target/arm: Implement BFCVTN for SVE
target/arm: Implement FCVTN (16- to 8-bit fp) for AdvSIMD
target/arm: Implement FCVTN, FCVTN2 (32- to 8-bit fp) for AdvSIMD
target/arm: Implement FCVTN (16- to 8-bit fp) for SVE
target/arm: Implement FCVTNB, FCVTNT for SVE
target/arm: Implement FCVT (FP16 to FP8) for SME
target/arm: Implement FCVT, FCVTN (FP32 to FP8) for SME
target/arm: Implement LUTI2, LUTI4 for AdvSIMD
target/arm: Implement LUTI2, LUTI4 for SVE
target/arm: Enable FEAT_LUT for -cpu max
target/arm: Enable FEAT_FP8 for -cpu max
include/fpu/softfloat.h | 22 +-
target/arm/cpregs.h | 5 +
target/arm/cpu-features.h | 66 +++
target/arm/cpu.h | 52 +--
target/arm/helper-fp8.h | 14 +
target/arm/internals.h | 13 +-
target/arm/tcg/helper-a64-defs.h | 11 +
target/arm/tcg/helper-defs.h | 5 +
target/arm/tcg/helper-fp8-defs.h | 25 ++
target/arm/tcg/helper-sme-defs.h | 2 +-
target/arm/tcg/helper-sve-defs.h | 14 +
target/arm/tcg/translate-a64.h | 1 +
target/arm/tcg/translate.h | 10 +
target/arm/tcg/vec_internal.h | 19 +
target/arm/vector-type.h | 44 ++
fpu/softfloat.c | 73 ++-
target/arm/helper.c | 43 +-
target/arm/machine.c | 20 +
target/arm/tcg/cpu64.c | 13 +
target/arm/tcg/fp8_helper.c | 742 +++++++++++++++++++++++++++++++
target/arm/tcg/hflags.c | 41 ++
target/arm/tcg/sme_helper.c | 8 +-
target/arm/tcg/sve_helper.c | 8 +
target/arm/tcg/translate-a64.c | 133 ++++++
target/arm/tcg/translate-sme.c | 85 +++-
target/arm/tcg/translate-sve.c | 111 +++++
target/arm/tcg/vec_helper.c | 52 +++
target/arm/tcg/vec_helper64.c | 51 +++
docs/system/arm/emulation.rst | 4 +
target/arm/cpu-sysregs.h.inc | 2 +
target/arm/tcg/a64.decode | 23 +
target/arm/tcg/meson.build | 1 +
target/arm/tcg/sme.decode | 28 +-
target/arm/tcg/sve.decode | 29 +-
34 files changed, 1691 insertions(+), 79 deletions(-)
create mode 100644 target/arm/helper-fp8.h
create mode 100644 target/arm/tcg/helper-fp8-defs.h
create mode 100644 target/arm/vector-type.h
create mode 100644 target/arm/tcg/fp8_helper.c
--
2.43.0