include/tcg/tcg-op-gvec.h | 24 ------------------------ 1 file changed, 24 deletions(-)
No code uses the tcg_gen_vec_*_tl() API. Better to
remove it now, since to compile as translation unit
files once we need to avoid target_ulong uses.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
Now this file only defines tcg_gen_gvec_dup_tl(), which
is used only once in target/riscv/insn_trans/trans_rvv.c.inc:
2156 static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
2157 {
2158 if (require_rvv(s) &&
2159 vext_check_isa_ill(s) &&
2160 /* vmv.v.x has rs2 = 0 and vm = 1 */
2161 vext_check_ss(s, a->rd, 0, 1)) {
2162 TCGv s1;
2163
2164 s1 = get_gpr(s, a->rs1, EXT_SIGN);
2165
2166 if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
2167 if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
2168 TCGv_i64 s1_i64 = tcg_temp_new_i64();
2169 tcg_gen_ext_tl_i64(s1_i64, s1);
2170 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
2171 MAXSZ(s), MAXSZ(s), s1_i64);
2172 } else {
2173 tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
^^^^^^^^^^^^^^^^^^^
2174 MAXSZ(s), MAXSZ(s), s1);
2175 }
2176 } else {
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Chao Liu <chao.liu.zevorn@gmail.com>
Cc: qemu-riscv@nongnu.org
---
include/tcg/tcg-op-gvec.h | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index b0a81ad4bf4..d82ba6dfaac 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -16,32 +16,8 @@
#if TARGET_LONG_BITS == 64
#define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
-#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64
-#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64
-#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64
-#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64
-#define tcg_gen_vec_add32_tl tcg_gen_vec_add32_i64
-#define tcg_gen_vec_sub32_tl tcg_gen_vec_sub32_i64
-#define tcg_gen_vec_shl8i_tl tcg_gen_vec_shl8i_i64
-#define tcg_gen_vec_shr8i_tl tcg_gen_vec_shr8i_i64
-#define tcg_gen_vec_sar8i_tl tcg_gen_vec_sar8i_i64
-#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i64
-#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i64
-#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i64
#elif TARGET_LONG_BITS == 32
#define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
-#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32
-#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32
-#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32
-#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32
-#define tcg_gen_vec_add32_tl tcg_gen_add_i32
-#define tcg_gen_vec_sub32_tl tcg_gen_sub_i32
-#define tcg_gen_vec_shl8i_tl tcg_gen_vec_shl8i_i32
-#define tcg_gen_vec_shr8i_tl tcg_gen_vec_shr8i_i32
-#define tcg_gen_vec_sar8i_tl tcg_gen_vec_sar8i_i32
-#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i32
-#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i32
-#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i32
#else
# error
#endif
--
2.53.0
On 4/23/26 20:19, Philippe Mathieu-Daudé wrote: > No code uses the tcg_gen_vec_*_tl() API. Better to > remove it now, since to compile as translation unit > files once we need to avoid target_ulong uses. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > Now this file only defines tcg_gen_gvec_dup_tl(), which > is used only once in target/riscv/insn_trans/trans_rvv.c.inc: Queued to tcg-next. r~
On 4/23/2026 3:19 AM, Philippe Mathieu-Daudé wrote:
> No code uses the tcg_gen_vec_*_tl() API. Better to
> remove it now, since to compile as translation unit
> files once we need to avoid target_ulong uses.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> Now this file only defines tcg_gen_gvec_dup_tl(), which
> is used only once in target/riscv/insn_trans/trans_rvv.c.inc:
>
> 2156 static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> 2157 {
> 2158 if (require_rvv(s) &&
> 2159 vext_check_isa_ill(s) &&
> 2160 /* vmv.v.x has rs2 = 0 and vm = 1 */
> 2161 vext_check_ss(s, a->rd, 0, 1)) {
> 2162 TCGv s1;
> 2163
> 2164 s1 = get_gpr(s, a->rs1, EXT_SIGN);
> 2165
> 2166 if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
> 2167 if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
> 2168 TCGv_i64 s1_i64 = tcg_temp_new_i64();
> 2169 tcg_gen_ext_tl_i64(s1_i64, s1);
> 2170 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> 2171 MAXSZ(s), MAXSZ(s), s1_i64);
> 2172 } else {
> 2173 tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
> ^^^^^^^^^^^^^^^^^^^
> 2174 MAXSZ(s), MAXSZ(s), s1);
> 2175 }
> 2176 } else {
>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> Cc: Weiwei Li <liwei1518@gmail.com>
> Cc: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> Cc: Chao Liu <chao.liu.zevorn@gmail.com>
> Cc: qemu-riscv@nongnu.org
> ---
> include/tcg/tcg-op-gvec.h | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
On 4/23/26 20:19, Philippe Mathieu-Daudé wrote:
> No code uses the tcg_gen_vec_*_tl() API. Better to
> remove it now, since to compile as translation unit
> files once we need to avoid target_ulong uses.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> Now this file only defines tcg_gen_gvec_dup_tl(), which
> is used only once in target/riscv/insn_trans/trans_rvv.c.inc:
>
> 2156 static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> 2157 {
> 2158 if (require_rvv(s) &&
> 2159 vext_check_isa_ill(s) &&
> 2160 /* vmv.v.x has rs2 = 0 and vm = 1 */
> 2161 vext_check_ss(s, a->rd, 0, 1)) {
> 2162 TCGv s1;
> 2163
> 2164 s1 = get_gpr(s, a->rs1, EXT_SIGN);
> 2165
> 2166 if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
> 2167 if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
> 2168 TCGv_i64 s1_i64 = tcg_temp_new_i64();
> 2169 tcg_gen_ext_tl_i64(s1_i64, s1);
> 2170 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> 2171 MAXSZ(s), MAXSZ(s), s1_i64);
> 2172 } else {
> 2173 tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
> ^^^^^^^^^^^^^^^^^^^
> 2174 MAXSZ(s), MAXSZ(s), s1);
> 2175 }
> 2176 } else {
>
> Cc: Palmer Dabbelt<palmer@dabbelt.com>
> Cc: Alistair Francis<alistair.francis@wdc.com>
> Cc: Weiwei Li<liwei1518@gmail.com>
> Cc: Daniel Henrique Barboza<daniel.barboza@oss.qualcomm.com>
> Cc: Liu Zhiwei<zhiwei_liu@linux.alibaba.com>
> Cc: Chao Liu<chao.liu.zevorn@gmail.com>
> Cc:qemu-riscv@nongnu.org
> ---
> include/tcg/tcg-op-gvec.h | 24 ------------------------
> 1 file changed, 24 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
On 4/23/2026 7:19 AM, Philippe Mathieu-Daudé wrote:
> No code uses the tcg_gen_vec_*_tl() API. Better to
> remove it now, since to compile as translation unit
> files once we need to avoid target_ulong uses.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Now this file only defines tcg_gen_gvec_dup_tl(), which
> is used only once in target/riscv/insn_trans/trans_rvv.c.inc:
>
> 2156 static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> 2157 {
> 2158 if (require_rvv(s) &&
> 2159 vext_check_isa_ill(s) &&
> 2160 /* vmv.v.x has rs2 = 0 and vm = 1 */
> 2161 vext_check_ss(s, a->rd, 0, 1)) {
> 2162 TCGv s1;
> 2163
> 2164 s1 = get_gpr(s, a->rs1, EXT_SIGN);
> 2165
> 2166 if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
> 2167 if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
> 2168 TCGv_i64 s1_i64 = tcg_temp_new_i64();
> 2169 tcg_gen_ext_tl_i64(s1_i64, s1);
> 2170 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> 2171 MAXSZ(s), MAXSZ(s), s1_i64);
> 2172 } else {
> 2173 tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
> ^^^^^^^^^^^^^^^^^^^
> 2174 MAXSZ(s), MAXSZ(s), s1);
> 2175 }
> 2176 } else {
>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> Cc: Weiwei Li <liwei1518@gmail.com>
> Cc: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> Cc: Chao Liu <chao.liu.zevorn@gmail.com>
> Cc: qemu-riscv@nongnu.org
> ---
> include/tcg/tcg-op-gvec.h | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index b0a81ad4bf4..d82ba6dfaac 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -16,32 +16,8 @@
>
> #if TARGET_LONG_BITS == 64
> #define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
> -#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64
> -#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64
> -#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64
> -#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64
> -#define tcg_gen_vec_add32_tl tcg_gen_vec_add32_i64
> -#define tcg_gen_vec_sub32_tl tcg_gen_vec_sub32_i64
> -#define tcg_gen_vec_shl8i_tl tcg_gen_vec_shl8i_i64
> -#define tcg_gen_vec_shr8i_tl tcg_gen_vec_shr8i_i64
> -#define tcg_gen_vec_sar8i_tl tcg_gen_vec_sar8i_i64
> -#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i64
> -#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i64
> -#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i64
> #elif TARGET_LONG_BITS == 32
> #define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
> -#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32
> -#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32
> -#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32
> -#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32
> -#define tcg_gen_vec_add32_tl tcg_gen_add_i32
> -#define tcg_gen_vec_sub32_tl tcg_gen_sub_i32
> -#define tcg_gen_vec_shl8i_tl tcg_gen_vec_shl8i_i32
> -#define tcg_gen_vec_shr8i_tl tcg_gen_vec_shr8i_i32
> -#define tcg_gen_vec_sar8i_tl tcg_gen_vec_sar8i_i32
> -#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i32
> -#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i32
> -#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i32
> #else
> # error
> #endif
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