Implement FEAT_FP8, the 8-bit conversion operations, and two prerequites.

Just now as I was writing the cover letter, I saw that FEAT_LUT is not yet
implemented.  The LUT instructions that I implemented before were just for
SME2, but FEAT_LUT is more that that.  Not really relevant to reviewing the
FP8 stuff, but something else that needs doing before enabling FEAT_FP8 at
the end.

There are lots more FP8 extensions, but this is large enough already.


r~


Richard Henderson (37):
  target/arm: Implement ID_AA64ISAR3
  target/arm: Implement FEAT_FAMINMAX for AdvSIMD
  target/arm: Implement FEAT_FAMINMAX for SME
  target/arm: Implement FEAT_FAMINMAX for SVE
  target/arm: Enable FEAT_FAMINMAX for -cpu max
  target/arm: Update SCR bits for Arm ARM M.a.a
  target/arm: Update HCRX bits for Arm ARM M.a.a
  target/arm: Introduce FPMR
  target/arm: Update SCTLR bits for FEAT_FPMR
  target/arm: Enable EnFPM bits for FEAT_FPMR
  target/arm: Clear FPMR on ResetSVEState
  target/arm: Add FPMR_EL to TBFLAGS
  target/arm: Trap direct acceses to FPMR
  target/arm: Enable FEAT_FPMR for -cpu max
  target/arm: Implement ID_AA64FPFR0
  target/arm: Add isar_feature_aa64_f8cvt
  target/arm: Implement FSCALE for AdvSIMD
  target/arm: Implement FSCALE for SME
  fpu: Add scalbn argument to fp8 conversion routines
  fpu: Add conversions between float16 and float8 formats
  target/arm: Split vector-type.h from cpu.h
  target/arm: Move vectors_overlap to vec_internal.h
  target/arm: Implement BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 for AdvSIMD
  target/arm: Implement BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT for SVE
  target/arm: Rename SME BFCVT patterns to BFCVT_hs
  target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME
  target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD
  target/arm: Implement F1CVT, F1CVTLT, F2CVT, F2CVTLT for SVE
  target/arm: Implement F1CVT, F1CVTL, F2CVT, F2CVTL for SME
  target/arm: Implement BFCVTN for SVE
  target/arm: Implement FCVTN (16- to 8-bit fp) for AdvSIMD
  target/arm: Implement FCVTN, FCVTN2 (32- to 8-bit fp) for AdvSIMD
  target/arm: Implement FCVTN (16- to 8-bit fp) for SVE
  target/arm: Implement FCVTNB, FCVTNT for SVE
  target/arm: Implement FCVT (FP16 to FP8) for SME
  target/arm: Implement FCVT, FCVTN (FP32 to FP8) for SME
  target/arm: Enable FEAT_FP8 for -cpu max

 include/fpu/softfloat.h          |  22 +-
 target/arm/cpregs.h              |   5 +
 target/arm/cpu-features.h        |  60 +++
 target/arm/cpu.h                 |  52 +--
 target/arm/helper-fp8.h          |  14 +
 target/arm/internals.h           |  13 +-
 target/arm/tcg/helper-a64-defs.h |  11 +
 target/arm/tcg/helper-fp8-defs.h |  25 ++
 target/arm/tcg/helper-sme-defs.h |   2 +-
 target/arm/tcg/helper-sve-defs.h |  14 +
 target/arm/tcg/translate-a64.h   |   1 +
 target/arm/tcg/translate.h       |   2 +
 target/arm/tcg/vec_internal.h    |  19 +
 target/arm/vector-type.h         |  44 ++
 fpu/softfloat.c                  |  73 ++-
 target/arm/helper.c              |  43 +-
 target/arm/machine.c             |  20 +
 target/arm/tcg/cpu64.c           |  12 +
 target/arm/tcg/fp8_helper.c      | 742 +++++++++++++++++++++++++++++++
 target/arm/tcg/hflags.c          |  41 ++
 target/arm/tcg/sme_helper.c      |   8 +-
 target/arm/tcg/sve_helper.c      |   8 +
 target/arm/tcg/translate-a64.c   |  94 ++++
 target/arm/tcg/translate-sme.c   |  85 +++-
 target/arm/tcg/translate-sve.c   |  43 ++
 target/arm/tcg/vec_helper64.c    |  51 +++
 docs/system/arm/emulation.rst    |   3 +
 target/arm/cpu-sysregs.h.inc     |   2 +
 target/arm/tcg/a64.decode        |  17 +
 target/arm/tcg/meson.build       |   1 +
 target/arm/tcg/sme.decode        |  28 +-
 target/arm/tcg/sve.decode        |  18 +
 32 files changed, 1495 insertions(+), 78 deletions(-)
 create mode 100644 target/arm/helper-fp8.h
 create mode 100644 target/arm/tcg/helper-fp8-defs.h
 create mode 100644 target/arm/vector-type.h
 create mode 100644 target/arm/tcg/fp8_helper.c

-- 
2.43.0