[v3] FEAT_RME_GDI initial work

[PATCH v3 0/4] FEAT_RME_GDI initial work

Jim MacArthur posted 4 patches 1 month, 1 week ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260421-jmac-feat._5Frme._5Fgdi-v3-0-ecd20c77eae1@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

target/arm/cpu-features.h          |  8 +++++++
target/arm/cpu.h                   |  5 +++++
target/arm/ptw.c                   | 20 +++++++++++++++++
tests/tcg/aarch64/system/rme_gdi.c | 46 ++++++++++++++++++++++++++++++++++++++
4 files changed, 79 insertions(+)

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[PATCH v3 0/4] FEAT_RME_GDI initial work

Posted by Jim MacArthur 1 month, 1 week ago

Adds FEAT_RME_GDI, some extra cases to arm_granule_protection_check,
and a very basic TCG test to check the prerequisites of FEAT_RME_GDI:
FEAT_RME and FEAT_RME_GPC2.

FEAT_RME_GDI is not enabled yet as no functional support has been
added; it can easily be enabled in cpu_arm_set_rme in future.

In the future we should correctly set bits in the fault address
registers such as PFAR_EL2, but I don't see any apparent support for
these in the existing GPT mechanism. Testing this also gets tricky as
I think this would have to be done from EL3 (e.g. by modifying
test_rme_virt.py)

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
Changes in v3:
- Test logic changed to accept any level of RMEGDI >= 1.

Changes in v2:
- arm_granule protection_check now checks SA, NSP, NA6, NA7 and
  goes to fault_fail if set for the appropriate GDI encoding.
- New fields for GPCCR: SA, NSP, NA6, NA7 and GPCBW
- Since we're touching AA64MMFR4, added in all the new fields not
  currently listed.
- Link to v1: https://lore.kernel.org/qemu-devel/20260416-jmac-feat_rme_gdi-v1-0-d9fa0781ed58@linaro.org

---
Jim MacArthur (4):
      target/arm/cpu-features.c: New fields in AA64MMFR4
      target/arm/cpu.h: New GPCCR fields
      target/arm/ptw.c: Add GDI spaces to the granule protection case
      tests/tcg/aarch64/system/rme_gdi.c: Very basic test of GDI

 target/arm/cpu-features.h          |  8 +++++++
 target/arm/cpu.h                   |  5 +++++
 target/arm/ptw.c                   | 20 +++++++++++++++++
 tests/tcg/aarch64/system/rme_gdi.c | 46 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 79 insertions(+)
---
base-commit: da6c4fe60fee30dd77267764d55b38af9cb89d4b
change-id: 20260416-jmac-feat_rme_gdi-71c2d2dd6770

Best regards,
-- 
Jim MacArthur <jim.macarthur@linaro.org>

Re: [PATCH v3 0/4] FEAT_RME_GDI initial work

Posted by Peter Maydell 1 month ago

On Tue, 21 Apr 2026 at 15:22, Jim MacArthur <jim.macarthur@linaro.org> wrote:
>
> Adds FEAT_RME_GDI, some extra cases to arm_granule_protection_check,
> and a very basic TCG test to check the prerequisites of FEAT_RME_GDI:
> FEAT_RME and FEAT_RME_GPC2.
>
> FEAT_RME_GDI is not enabled yet as no functional support has been
> added; it can easily be enabled in cpu_arm_set_rme in future.
>
> In the future we should correctly set bits in the fault address
> registers such as PFAR_EL2, but I don't see any apparent support for
> these in the existing GPT mechanism. Testing this also gets tricky as
> I think this would have to be done from EL3 (e.g. by modifying
> test_rme_virt.py)
>
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>

(cover letters don't need signed-off-by tags, just fyi)


Applied to target-arm.next, thanks.

-- PMM