This rolls over my previous series posted earlier in this mailing list.
..and adds some more.
Git tree: https://github.com/mediouni-m/qemu whpx-i386-202604-4
Some highlights:
1
- user-mode x2APIC emulation (kernel-irqchip=off) for better
performance when it has to be used.
- CPU model emulation on both Windows 10 and 11
- configurable behavior for unknown MSRs and adding a way
to trap on GPFs raised by Hyper-V on MSR acccess
- when -M hyperv=off, report the hypervisor as VMware for
guests to use either the VMware CPUID leaf or the vmport
interface to get the TSC and APIC frequencies.
If the vmware CPUID frequency leaf is disabled, then KVM
is reported.
- xsave save/restore support
- Pause the VM to be able to inspect state on a fatal fault
instead of just exiting
- adding emulation of an oddball idle MSR used by Windows
when kernel-irqchip=off.
- disable kernel-irqchip and Hyper-V enlightenments for
isapc
- for Windows 10, change the default to an emulated x2APIC
(kernel-irqchip=off). The recommended way to use the Hyper-V
LAPIC is not to use -M kernel-irqchip=on, but -M pic=off.
And as the last commit, a documentation update.
Bug reports and patches are welcome.
However, due to reasons, I'll probably step aside
from this all for a bit so don't expect immediate replies.
v1->v2:
- Build fixup for macOS and OpenBSD
- a bit of cleanup
Magnus Kulke (1):
target/i386: add de/compaction to xsave_helper
Mohamed Mediouni (37):
target/i386: emulate: include name of unhandled instruction
whpx: i386: x2apic emulation
whpx: i386: wire up feature probing
whpx: i386: disable TbFlushHypercalls for emulated LAPIC
whpx: i386: enable x2apic by default for user-mode LAPIC
whpx: i386: reintroduce enlightenments for Windows 10
whpx: i386: introduce proper cpuid support
whpx: i386: kernel-irqchip=off fixes
whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off
whpx: i386: disable kernel-irqchip on Windows 10 when PIC enabled
whpx: i386: IO port fast path cleanup
whpx: i386: disable enlightenments and LAPIC for isapc
whpx: i386: interrupt priority support
hw/intc: apic: disallow APIC reads when disabled
whpx: i386: fix CPUID[1:EDX].APIC reporting
whpx: i386: set apicbase value only on success
whpx: i386: unknown MSR configurability
whpx: i386: enable GuestIdleReg enlightenment
whpx: i386: tighten APIC base validity check
whpx: i386: ignore vpassist when kernel-irqchip=off
target: i386: HLT type that ignores EFLAGS.IF
whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip
whpx: i386: one more CPUID
whpx: i386: some x2APIC awareness
whpx: i386: set WHvX64RegisterInitialApicId
whpx: i386: Pause VM on fatal exception to be able to inspect state
target/i386: emulate: use exception_payload for fault address
whpx: i386: CPU features support for Windows 10
target/i386: make xsave_buf present unconditionally
whpx: xsave support
whpx: i386: set APIC ID only when APIC present
whpx: i386: update migration blocker message
whpx: i386: don't increment eip on MSR access raising GPF
target/i386: emulate, hvf: rdmsr/wrmsr GPF handling
whpx: i386: add feature to intercept #GP MSR accesses
whpx: i386: intercept CPUID 0xD too
whpx: i386: documentation update
accel/whpx/whpx-common.c | 78 ++
docs/system/whpx.rst | 30 +-
hw/intc/apic.c | 9 +
include/system/whpx-common.h | 2 +-
include/system/whpx-internal.h | 28 +
target/arm/whpx/whpx-all.c | 1 +
target/i386/cpu.c | 25 +-
target/i386/cpu.h | 6 +-
target/i386/emulate/x86_emu.c | 14 +-
target/i386/emulate/x86_emu.h | 4 +-
target/i386/emulate/x86_mmu.c | 3 +-
target/i386/hvf/hvf.c | 9 +-
target/i386/whpx/meson.build | 1 +
target/i386/whpx/whpx-all.c | 1247 ++++++++++++++++++++++------
target/i386/whpx/whpx-apic.c | 83 +-
target/i386/whpx/whpx-cpu-legacy.c | 171 ++++
target/i386/whpx/whpx-i386.h | 11 +
target/i386/xsave_helper.c | 256 ++++++
18 files changed, 1696 insertions(+), 282 deletions(-)
create mode 100644 target/i386/whpx/whpx-cpu-legacy.c
create mode 100644 target/i386/whpx/whpx-i386.h
--
2.50.1 (Apple Git-155)